LPC3131

D D D R A FT D R A FT D R A FT R R A FT A FT www.DataSheet4U.com LPC3130/3131 Rev. 1.01 — 21 May 2009 D Low-cost, low-power ARM926EJ-S MCUs with high-speed USB 2.0 OTG, SD/MMC, and NAND flash controller D R R A A FT FT D R A FT D D R A FT D R A FT D FT D D R A R A FT D Preliminary data sheet FT D R R A R A FT D R A FT D R A F A FT D R D R 1. General description The NXP LPC3130/3131 combine an 180 MHz ARM926EJ-S CPU core, high-speed USB 2.0 On-The-Go (OTG), up to 192 KB SRAM, NAND flash controller, flexible external bus interface, four channel 10-bit ADC, and a myriad of serial and parallel interfaces in a single chip targeted at consumer, industrial, medical, and communication markets. To optimize system power consumption, the LPC3130/3131 have multiple power domains and a very flexible Clock Generation Unit (CGU) that provides dynamic clock gating and scaling. A FT D R A 2. Features 2.1 Key features „ CPU platform ‹ 180 MHz, 32-bit ARM926EJ-S ‹ 16 kB D-cache and 16 kB I-cache ‹ Memory Management Unit (MMU) „ Internal memory ‹ 96 kB (LPC3130) or 192 kB (LPC3131) embedded SRAM „ External memory interface ‹ NAND flash controller with 8-bit ECC ‹ 8/16-bit Multi-Port Memory Controller (MPMC): SDRAM and SRAM „ Communication and connectivity ‹ High-speed USB 2.0 (OTG, Host, Device) with on-chip PHY ‹ Two I2S-bus interfaces ‹ Integrated master/slave SPI ‹ Two master/slave I2C-bus interfaces ‹ Fast UART ‹ Memory Card Interface (MCI): MMC/SD/SDIO/CE-ATA ‹ Four-cha...