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STP12N65M5 Dataheets PDF



Part Number STP12N65M5
Manufacturers ST Microelectronics
Logo ST Microelectronics
Description N-Channel Power MOSFET
Datasheet STP12N65M5 DatasheetSTP12N65M5 Datasheet (PDF)

STF12N65M5, STP12N65M5 Datasheet N-channel 650 V, 390 mΩ typ., 8.5 A MDmesh M5 Power MOSFET in a TO-220FP and TO-220 packages TAB 123 TO-220FP 123 TO-220 D(2, TAB) Features Order code VDS @ TJ max. RDS(on) max. STF12N65M5 STP12N65M5 710 V 430 mΩ • Extremely low RDS(on) • Low gate charge and input capacitance • Excellent switching performance • 100% avalanche tested ID 8.5 A G(1) S(3) Applications • Switching applications AM01475v1_noZen Description This device is an N-channel Po.

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STF12N65M5, STP12N65M5 Datasheet N-channel 650 V, 390 mΩ typ., 8.5 A MDmesh M5 Power MOSFET in a TO-220FP and TO-220 packages TAB 123 TO-220FP 123 TO-220 D(2, TAB) Features Order code VDS @ TJ max. RDS(on) max. STF12N65M5 STP12N65M5 710 V 430 mΩ • Extremely low RDS(on) • Low gate charge and input capacitance • Excellent switching performance • 100% avalanche tested ID 8.5 A G(1) S(3) Applications • Switching applications AM01475v1_noZen Description This device is an N-channel Power MOSFET based on the MDmesh M5 innovative vertical process technology combined with the well-known PowerMESH horizontal layout. The resulting product offers extremely low on-resistance, making it particularly suitable for applications requiring high power and superior efficiency. Product status links STF12N65M5 STP12N65M5 Product summary Order code STF12N65M5 Marking 12N65M5 Package TO-220FP Packing Tube Order code STP12N65M5 Marking 12N65M5 Package TO-220 Packing Tube DS6117 - Rev 6 - March 2022 For further information contact your local STMicroelectronics sales office. www.st.com STF12N65M5, STP12N65M5 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter VDS Drain-source voltage VGS Gate-source voltage Drain current (continuous) at TC = 25 °C ID Drain current (continuous) at TC = 100 °C IDM(2) Drain current (pulsed) PTOT Total power dissipation at TC = 25 °C IAR Avalanche current, repetitive or not repetitive (pulse width limited by TJ max.) EAS Single pulse avalanche energy (starting TJ = 25 °C, ID = IAR, VDD = 50 V) dv/dt(3) Peak diode recovery voltage slope VISO Insulation withstand voltage (RMS) from all three leads to external heat sink (t = 1 s, TC = 25 °C) Tstg Storage temperature range TJ Operating junction temperature range 1. Limited by maximum junction temperature. 2. Pulse width is limited by safe operating area. 3. ISD ≤ 8.5 A, di/dt ≤ 400 A/μs, VDS (peak) < V(BR)DSS, VDD = 400 V. Value Unit TO-220FP TO-220 650 V 25 V 8.5(1) 5.4(1) 8.5 A 5.4 34 34 A 25 70 W 2.5 A 150 mJ 15 V/ns 2.5 kV °C -55 to 150 °C Table 2. Thermal data Symbol Parameter RthJC RthJA Thermal resistance, junction-to-case Thermal resistance, junction-to-ambient Value Unit TO-220FP TO-220 5.00 1.79 °C/W 62.5 °C/W DS6117 - Rev 6 page 2/15 STF12N65M5, STP12N65M5 Electrical characteristics 2 Electrical characteristics TC = 25 °C unless otherwise specified. Table 3. On/off states Symbol Parameter Test conditions V(BR)DSS Drain-source breakdown voltage VGS = 0 V, ID = 1 mA IDSS Zero gate voltage drain current VGS = 0 V, VDS = 650 V VGS = 0 V, VDS = 650 V, TC = 125 °C(1) IGSS Gate-body leakage current VDS = 0 V, VGS = ±25 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 4.3 A 1. Specified by design, not tested in production. Min. Typ. Max. Unit 650 V 1 µA 100 100 nA 3 4 5 V 390 430 mΩ Table 4. Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit Ciss Input capacitance - 900 - pF Coss Output capacitance VDS = 100 V, f = 1 MHz, VGS = 0 V - 22 - pF Crss Reverse transfer capacitance - 2 - pF Co(tr)(1) Co(er)(2) Equivalent capacitance time related Equivalent capacitance energy related VDS = 0 to 520 V, VGS = 0 V - 64 - pF - 21 - pF Rg Intrinsic gate resistance f = 1 MHz, ID = 0 A - 5 - Ω Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge VDD = 520 V, ID = 4.25 A, VGS = 0 to 10 V - 20 - nC (see Figure 17. Test circuit for gate - 4.8 - nC charge behavior) - 8.3 - nC 1. Co(tr) is an equivalent capacitance that provides the same charging time as Coss while VDS is rising from 0 V to the stated value. 2. Co(er) is an equivalent capacitance that provides the same stored energy as Coss while VDS is rising from 0 V to the stated value. Symbol td(v) tr(v) tf(i) tc(off) Parameter Voltage delay time Voltage rise time Current fall time Crossing time Table 5. Switching times Test conditions VDD = 400 V, ID = 5 A, RG = 4.7 Ω, VGS = 10 V (see Figure 18. Test circuit for inductive load switching and diode recovery times and Figure 21. Switching time waveform) Min. - Typ. Max. Unit 22.6 - ns 17.6 - ns 15.6 - ns 23.4 - ns DS6117 - Rev 6 page 3/15 STF12N65M5, STP12N65M5 Electrical characteristics Table 6. Source-drain diode Symbol Parameter Test conditions ISD Source-drain current ISDM(1) Source-drain current (pulsed) VSD(2) trr Qrr IRRM Forward on voltage Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 8.5 A, VGS = 0 V ISD = 8.5 A, di/dt = 100 A/µs, VDD = 100 V (see Figure 18. Test circuit for inductive load switching and diode recovery times) trr Qrr IRRM Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 8.5 A, di/dt = 100 A/µs, VDD = 100 V, .


STD12N65M5 STP12N65M5 STF12N65M5


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