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CDRM622 Dataheets PDF



Part Number CDRM622
Manufacturers Agere Systems
Logo Agere Systems
Description 622 Mbits/s Multichannel Digital Timing Recovery
Datasheet CDRM622 DatasheetCDRM622 Datasheet (PDF)

Data Sheet June 1999 www.DataSheet4U.com CDRM622 622 Mbits/s Multichannel Digital Timing Recovery Features s Description The CDRM622 provides a physical medium for highspeed asynchronous serial data transfer between ASIC devices. Devices can be on the same PCboard, or on separate boards connected across a backplane, or connected by cables. The macrocell is intended for, but not limited to, terminal equipment in SONET/SDH and ATM systems. The macrocell consists of three functional blocks. The r.

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Data Sheet June 1999 www.DataSheet4U.com CDRM622 622 Mbits/s Multichannel Digital Timing Recovery Features s Description The CDRM622 provides a physical medium for highspeed asynchronous serial data transfer between ASIC devices. Devices can be on the same PCboard, or on separate boards connected across a backplane, or connected by cables. The macrocell is intended for, but not limited to, terminal equipment in SONET/SDH and ATM systems. The macrocell consists of three functional blocks. The receiver accepts 622.08 Mbits/s serial data. Based on data transitions, the receiver selects an appropriate 622 MHz clock phase for each channel to retime the data, then demultiplexes down to 77.76 Mbytes/s parallel bytes and a 77.76 MHz clock. The transmitter operates in the reverse direction. 77.76 Mbytes/s parallel bytes are multiplexed up to 662.08 Mbits/s serial data for off-chip communication. The clock synthesizer generates the necessary 622.08 MHz clock for operation from a 77.76 MHz reference. Figure 1 illustrates the function of the macrocell. The hard macrocell can be supplied for up to 16 data channels. Multiple macrocells can be used on a single device. The macrocell is intended to be used with high-speed differential I/O buffers for the 622 Mbits/s serial data streams and the 77.76 MHz reference clock. Common selections are low-voltage differential swing (LVDS) or PECL. The I/O buffers are part of our standard-cell ASIC library and are not included in the macrocell to allow for flexibility. Receives scrambled serial data at STS-12/STM-4 (622.08 Mbits/s) rate. Demultiplexes serial data to 77.76 Mbytes/s parallel byte wide data with aligned 77.76 MHz clock. Synthesizes 622.06 MHz clock with on-chip PLL, requiring only 77.76 MHz input reference clock and one external resistor. Multiplexes parallel 77.76 Mbytes/s data to 622 Mbits/s serial data for transmission. Incorporates n = 1 to 16 channels with modular design. Implemented in Lucent Technologies Microelectronics Group HL250C technology. Meets type B jitter tolerance specification of ITU-T Recommendation G.958. Sources stable clock in absence of data transitions once the clock synthesizer has acquired lock. Uses single, low-voltage (3.3 V ± 5%) supply. Includes built-in test circuitry such as high-speed loopback of transmit data into receiver. IDDQ compatible. Powers down the receiver on per-channel basis. Allows JTAG access to high-speed data paths. s s s s s s s s s s s CDRM622 622 Mbits/s Multichannel Digital Timing Recovery Macrocell www.DataSheet4U.com Data Sheet June 1999 Description (continued) MRESET (MASTER RESET) TSTMODE TSTSHFTLD ECSEL EXDNUP ETOGGLE TSTPHASE BUILT-IN TEST TSTMUX[8:0] Rx TSTCLK BYPASS LOOPBKEN LOOPBKCH[(n – 1):0] HDIN[(n – 1):0] 622 Mbits/s DATA CDR CLOCK/DATA ALIGNMENT RETIME SELECT SERIAL TO PARRALLEL (622 Mbits/s TO 78 Mbytes/s) DEMUX 1 2 n BSIPAD[(n – 1):0] (BOUNDARY SCAN) LD[(n – 1):0]R[7:0] 77.76 Mbytes/s LCKR[(n – 1):0] 77.76 MHz RESETRN (TEST) RXPWRDN[(n – 1):0] REXT PLLPWRDN REF78 77.76 MHz 622.08 MHz SYNTHESIZER PLL LCK78 77.76 MHz TSTCLK BYPASS Tx MUX PARRALLEL TO SERIAL (78 Mbytes/s TO 622 Mbits/s) BOUNDARY SCAN LDAT[(n – 1):0] X[7:0] 77.76 Mbytes/s HDOUT[(n –1):0] 622 Mbits/s DATA BSOPAD[(n – 1):0] 1 BSCANEN RESETTN (TEST) 5-5833 (F).br.2 2 (BOUNDARY SCAN) n Figure 1. CDRM622 Block Diagram 2 Lucent Technologies Inc. Data Sheet June 1999 www.DataSheet4U.com CDRM622 622 Mbits/s Multichannel Digital Timing Recovery Macrocell Description (continued) Physical Size The macrocell is able to support up to 16 channels of serial data; however, the physical design will be limited to two sizes (8 and 16). Unused receivers will be powered down for specific applications as the physical size of the macrocell does not vary directly with channels. The physical dimensions of a 16-channel macrocell are approximately square at 2.2 mm per side. Power Dissipation At 3.3 V, power is estimated by 300 mW + 50 mW per Rx channel + 10 mW per Tx channel. Device IO Buffers Device IO buffers are not part of the hard macrocell. This allows customers to choose the most appropriate interface levels without disturbing the macrocell. Common choices of device interface levels are LVDS (low-voltage differential swing) and PECL. Device pinout is also flexible. Appropriate buffering will be added to the device by Lucent Technologies Microelectronics Group to ensure data integrity between the IO buffers and the macrocell. Lucent Technologies Inc. 3 CDRM622 622 Mbits/s Multichannel Digital Timing Recovery Macrocell www.DataSheet4U.com Data Sheet June 1999 Hardware Interface Table 1. Functional Signals Signal Name HDIN[(n – 1):0] LD[(n – 1):0]R[7:0] LCKR[(n – 1):0] LCK78 Type I O O O Description 622.08 Mbits/s serial data inputs. One input for each independent data channel. Low-speed demultiplexed data bytes retimed to recovered 77.76 MHz clocks. Low-speed 77.76 MHz recovered clocks. Low-speed (77.76 MHz) PLL divi.


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