DatasheetsPDF.com

74AUP1T57 Dataheets PDF



Part Number 74AUP1T57
Manufacturers NXP
Logo NXP
Description Low-power Configurable Gate
Datasheet 74AUP1T57 Datasheet74AUP1T57 Datasheet (PDF)

www.DataSheet4U.com 74AUP1T57 Low-power configurable gate with voltage-level translator Rev. 01 — 3 January 2008 Product data sheet 1. General description The 74AUP1T57 provides low-power, low-voltage configurable logic gate functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND, NOR, XNOR, inverter and buffer. All inputs can be connected to VCC or GND. This device ensures a very low static and dynamic power consumption a.

  74AUP1T57   74AUP1T57



Document
www.DataSheet4U.com 74AUP1T57 Low-power configurable gate with voltage-level translator Rev. 01 — 3 January 2008 Product data sheet 1. General description The 74AUP1T57 provides low-power, low-voltage configurable logic gate functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND, NOR, XNOR, inverter and buffer. All inputs can be connected to VCC or GND. This device ensures a very low static and dynamic power consumption across the entire VCC range from 2.3 V to 3.6 V. The 74AUP1T57 is designed for logic-level translation applications with input switching levels that accept 1.8 V low-voltage CMOS signals, while operating from either a single 2.5 V or 3.3 V supply voltage. The wide supply voltage range ensures normal operation as battery voltage drops from 3.6 V to 2.3 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across the entire VCC range. 2. Features s Wide supply voltage range from 2.3 V to 3.6 V s High noise immunity s ESD protection: x HBM JESD22-A114E Class 3A exceeds 5000 V x MM JESD22-A115-A exceeds 200 V x CDM JESD22-C101C exceeds 1000 V s Low static power consumption; ICC = 1.5 µA (maximum) s Latch-up performance exceeds 100 mA per JESD 78 Class II s Inputs accept voltages up to 3.6 V s Low noise overshoot and undershoot < 10 % of VCC s IOFF circuitry provides partial Power-down mode operation s Multiple package options s Specified from −40 °C to +85 °C and −40 °C to +125 °C www.DataSheet4U.com NXP Semiconductors 74AUP1T57 Low-power configurable gate with voltage-level translator 3. Ordering information Table 1. Ordering information Package Temperature range Name 74AUP1T57GW 74AUP1T57GM 74AUP1T57GF −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C SC-88 XSON6 XSON6 Description plastic surface-mounted package; 6 leads Version SOT363 Type number plastic extremely thin small outline package; no leads; SOT886 6 terminals; body 1 × 1.45 × 0.5 mm plastic extremely thin small outline package; no leads; SOT891 6 terminals; body 1 × 1 × 0.5 mm 4. Marking Table 2. Marking Marking code p7 p7 p7 Type number 74AUP1T57GW 74AUP1T57GM 74AUP1T57GF 5. Functional diagram 3 4 B 1 Y A C 6 001aab583 Fig 1. Logic symbol 74AUP1T57_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 3 January 2008 2 of 17 w w NXP Semiconductors w . D a t a S h e e t 4 U . c o m 74AUP1T57 Low-power configurable gate with voltage-level translator 6. Pinning information 6.1 Pinning 74AUP1T57 74AUP1T57 B GND 1 2 6 5 C GND VCC A A 3 001aah472 B 1 6 C B GND 74AUP1T57 1 2 3 6 5 4 C VCC Y 2 5 VCC 3 4 Y A 4 Y 001aah471 001aah473 Transparent top view Transparent top view Fig 2. Pin configuration SOT3.


FXL4245 74AUP1T57 74AUP1T58


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)