ADN4663

FEATURES ±15 kV ESD protection on output pins 600 Mbps (300 MHz) switching rates Flow-through pinout simplifies PCB layout 300 ps typical differential skew 700 ps maximum differential skew 1.5 ns maximum propagation delay 3.3 V power supply ±355 mV differential signaling Low power dissipation: 23 mW typical Interoperable with existing 5 V LVDS receivers Conforms to TIA/EIA-644 LVDS standard Industrial operating temperature range (−40°C to +85°C) Available in surface-mount (SOIC) package APPLICATIONS Backplane data transmission Cable data transmission Clock distribution GENERAL DESCRIPTION The ADN4663 is a dual, CMOS, low voltage differential signaling (LVDS) line driver offering data rates of over 600 Mbps (300 MHz), and ultralow power consumption. It features a flow-through pinout for easy PCB layout and separation of input and output signals. The device accepts low voltage TTL/CMOS logic signals and converts them to a differential current output of typically ±3.1 mA for driving a transmission medium such as a Dual, 3 V, CMOS, LVDS High Speed Differential Driver ADN4663 FUNCTIONAL BLOCK DIAGRAM VCC ADN4663 DIN1 DOUT1+ DOUT1– DIN2 DOUT2+ DOUT2– 07927-001 GND Figure 1. twisted-pair cable. The transmitted signal develops a differential voltage of typically ±355 mV across a termination resistor at the receiving end, and this is converted back to a TTL/CMOS logic level by a line receiver. The ADN4663 and a companion receiver offer a new solution to high speed point-to-p...