TMXA84622

Hardware Design Guide, Revision 1 February 21, 2003 TMXA84622 Ultramapper Full Transport 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1 www.datasheet4u.com 1 Introduction The last issue of this data sheet was November 27, 2002. A change history (since the last issue) is included in Section 12 Change History, on page 55. Red change bars have been installed on all text, figures, and tables that were added or changed. All changes to the text are highlighted in red. Changes within figures, and the figure title itself, are highlighted in red, if feasible. Formatting or grammatical changes have not been highlighted. Deleted sections, paragraphs, figures, or tables will be specifically mentioned. The documentation package for the TMXA84622 Full Transport 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1 system chip consists of the following documents: s The Register Description and the System Design Guide. These documents are available on a password-protected website. The Ultramapper Full Transport Product Description and the Ultramapper Full Transport Hardware Design Guide (this document). These documents are available on the public website shown below (select Mappers/MUXes): http://www.agere.com/enterprise_metro_access/index.html s This document describes the hardware interfaces to the Agere Systems TMXA84622 Ultramapper Full Transport device. Information relevant to the use of the device in a board design is covered. Pin descriptions, dc electrical characteristics, timing diagrams...