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10-Bit, 105 MSPS/125 MSPS/150 MSPS, 1.8 V Dual Analog-to-Digital Converter AD9600
FEATURES www.datasheet4u.com
SNR = 60.6 dBc (61.6 dBFS) to 70 MHz at 150 MSPS SFDR = 81 dBc to 70 MHz at 150 MSPS Low power: 825 mW at 150 MSPS 1.8 V analog supply operation 1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS supply Integer 1 to 8 input clock divider Intermediate frequency (IF) sampling frequencies up to 450 MHz Internal analog-to-digital converter (ADC) voltage reference Integrated ADC sample-and-hold inputs Flexible analog input: 1 V p-p to 2 V p-p range Differential analog inputs with 650 MHz bandwidth ADC clock duty cycle stabilizer 95 dB channel isolation/crosstalk Serial port control User-configurable built-in self-test (BIST) capability Energy-saving power-down modes Integrated receive features Fast detect/threshold bits Composite signal monitor I/Q demodulation systems Smart antenna systems Digital predistortion General-purpose software radios Broadband data applications Data acquisition Nondestructive testing
PRODUCT HIGHLIGHTS
1. 2. 3. 4. 5. Integrated dual, 10-bit, 150 MSPS/125 MSPS/105 MSPS ADC. Fast overrange detect and signal monitor with serial output. Signal monitor block with dedicated serial output mode. Proprietary differential input maintains excellent SNR performance for input frequencies up to 450 MHz. The AD9600 operates from a single 1.8 V supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families. A standard serial port interface supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down mode, and voltage reference mode. The AD9600 is pin compatible with the AD9627-11, AD9627, and AD9640, allowing a simple migration from 10 bits to 11 bits, 12 bits, or 14 bits.
6.
APPLICATIONS
Point-to-point radio receivers (GPSK, QAM) Diversity radio systems
7.
FUNCTIONAL BLOCK DIAGRAM
AVDD DVDD FD[0:3]A SDIO/ SCLK/ DCS DFS CSB DRVDD
AD9600
VIN + A SHA VIN – A VREF SENSE CML REFERENCE SELECT – +
FD BITS/THRESHOLD DETECT
SPI
CMOS/LVDS OUTPUT BUFFER
D9A D0A
PROGRAMMING DATA ADC DIVIDE 1 TO 8 SIGNAL MONITOR DUTY CYCLE STABLIZER
CLK+ CLK– DCO GENERATION
CMOS/LVDS OUTPUT BUFFER
DCOA DCOB
VIN – B SHA VIN + B
ADC SERIAL MONITOR DATA
D9B D0B
MULTICHIP SYNC
FD BITS/THRESHOLD DETECT
SERIAL MONITOR INTERFACE
AGND SYNC
FD[0:3]B
Figure 1.
Rev. 0
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06909-001
NOTES 1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY; SEE FIGURE 7 FOR LVDS PIN NAMES.
SMI SMI SMI SDFS SCLK/ SDO/ PDWN OEB
DRGND
AD9600 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1
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Peak Detector Mode................................................................... 32 RMS/MS Magnitude Mode....................................................... 32 Threshold Crossing Mode......................................................... 33 Additional Control Bits ............................................................. 33 DC Correction ............................................................................ 34 Signal Monitor SPORT Output ................................................ 34 Built-In Self-Test (BIST) and Output Test .................................. 35 Built-In Self-Test (BIST)............................................................ 35 Output Test Modes..................................................................... 35 Channel/Chip Synchronization.................................................... 36 Serial Port Interface (SPI).............................................................. 37 Configuration Using the SPI..................................................... 37 Hardware Interface..................................................................... 37 Configuration Without the SPI ................................................ 38 SPI Accessible Features.............................................................. 38 Memory Map .................................................................................. 39 Reading the Memory Map Table.............................................. 39 Memory Map ....................