MAX3620

19-3550; Rev 0; 1/05 Delay Lines for High-Speed Clock Distribution Systems General Description www.datasheet4u.com Features ♦ Supports HSTL Source Terminated Lines ♦ All-Passive Design ♦ Compatible with 100Ω Differential and 50Ω SingleEnded Transmission Lines ♦ Small 3mm x 3mm Package MAX3620 The MAX3620 series is a family of high-performance passive delay lines for use in QDR/QDRII synchronous memory systems. These delay lines support high-speed transceiver logic (HSTL) source terminated transmission with an unterminated load at the receiver, and deliver accurate delays of 0.75ns, 1.00ns, 1.25ns, and 1.50ns for the generation of the quarter clock phase. The MAX3620 is offered in a small 3mm x 3mm package which contains two delay lines of equal length that can be driven either differentially or single-endedly. Applications QDR/QDRII Memory Systems Multiphase Clock Generation PART MAX3620AETT MAX3620BETT MAX3620CETT MAX3620DETT Ordering Information TEMP RANGE -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C PIN-PACKAGE 6 TDFN 6 TDFN 6 TDFN 6 TDFN Pin Configuration TOP VIEW IN1 COMMON IN2 1 2 3 6 5 4 OUT1 COMMON OUT2 Selector Guide PART MAX3620AETT MAX3620BETT MAX3620CETT MAX3620DETT PKG CODE T633-2 T633-2 T633-2 T633-2 TOP MARK AJX AIY AIZ AJA MAX3620 *EP TDFN *EP—EXPOSED PAD. MUST BE CONNECTED TO THE SAME POTENTIAL AS COMMON. Typical Application Circuit QDR II SRAM CLOCK OUTPUT HSTL SOURCE TERMINATED 50Ω IN1 COMMON DELAY LINE 1/4 CLOCK PERIOD OUT1 C...