HYB25DC512160BE

www.datasheet4u.com April 2007 HYB25DC512800B[E/F] HYB25DC512160B[E/F] 512-Mbit Double-Data-Rate SDRAM DDR SDRAM RoHS Compliant Products Internet Data Sheet Rev. 1.2 www.datasheet4u.com Internet Data Sheet HYB25DC512[80/16]0B[E/F] Double-Data-Rate SDRAM HYB25DC512800B[E/F], HYB25DC512160B[E/F] Revision History: 2007-04, Rev. 1.2 Page All All All Subjects (major changes since last revision) Adapted internet edition Editorial changes Qimonda template update Previous Revision: 2006-09, Rev. 1.11 Previous Revision: 2006-09, Rev. 1.1 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: [email protected] qag_techdoc_rev400 / 3.2 QAG / 2006-08-07 04112007-FHBX-O8HD 2 www.datasheet4u.com Internet Data Sheet HYB25DC512[80/16]0B[E/F] Double-Data-Rate SDRAM 1 1.1 Overview Features This chapter lists all main features of the product family HYB25DC512[80/16]0B[E/F] and the ordering information. Double data rate architecture: two data transfers per clock cycle Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver DQS is edge-aligned with data for reads and is center-aligned with data for writes Differential clock inputs (CK and CK) Four internal banks for con...