CY7C1217F

CY7C1217F www.DataSheet4U.com 1-Mbit (32K x 36) Flow-Through Sync SRAM Features 32K x 36 common I/O 3.3V –5% and +10% core power supply (VDD) 3.3V I/O supply (VDDQ) Fast clock-to-output times — 7.5 ns (117-MHz version) — 8.0 ns (100-MHz version) Provide high-performance 2-1-1-1 access rate User-selectable burst counter supporting Pentium interleaved or linear burst sequences Separate processor and controller address strobes Synchronous self-timed write Asynchronous output enable Supports 3.3V I/O level Offered in JEDEC-standard 100-pin TQFP “ZZ” Sleep Mode option Intel 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BW[A:D], and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. The CY7C1217F allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC) inputs....