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CY7C1215H Dataheets PDF



Part Number CY7C1215H
Manufacturers Cypress Semiconductor
Logo Cypress Semiconductor
Description 1-Mbit (32K x 32) Pipelined Sync SRAM
Datasheet CY7C1215H DatasheetCY7C1215H Datasheet (PDF)

CY7C1215H www.DataSheet4U.com 1-Mbit (32K x 32) Pipelined Sync SRAM Features • Registered inputs and outputs for pipelined operation • 32K × 32 common I/O architecture • 3.3V core power supply (VDD) • 2.5V/3.3V I/O power supply (VDDQ) • Fast clock-to-output times — 3.5 ns (for 166-MHz device) • Provide high-performance 3-1-1-1 access rate • User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences • Separate processor and controller address strobes • Synchro.

  CY7C1215H   CY7C1215H


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CY7C1215H www.DataSheet4U.com 1-Mbit (32K x 32) Pipelined Sync SRAM Features • Registered inputs and outputs for pipelined operation • 32K × 32 common I/O architecture • 3.3V core power supply (VDD) • 2.5V/3.3V I/O power supply (VDDQ) • Fast clock-to-output times — 3.5 ns (for 166-MHz device) • Provide high-performance 3-1-1-1 access rate • User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed write • Asynchronous output enable • Offered in JEDEC-standard lead-free 100-pin TQFP package • “ZZ” Sleep Mode Option Functional Description[1] The CY7C1215H SRAM integrates 32K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BW[A:D], and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to four bytes wide as controlled by the Byte Write control inputs. GW when active LOW causes all bytes to be written. The CY7C1215H operates from a +3.3V core power supply while all outputs may operate either with a + 2.5V or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Logic Block Diagram A0, A1, A ADDRESS REGISTER 2 A[1:0] MODE ADV CLK Q1 ADSC ADSP BWD DQD BYTE WRITE REGISTER DQC BYTE WRITE REGISTER DQB BYTE WRITE REGISTER DQA BYTE WRITE REGISTER BURST COUNTER CLR AND Q0 LOGIC DQD BYTE WRITE DRIVER DQC BYTE WRITE DRIVER DQB BYTE WRITE DRIVER DQA BYTE WRITE DRIVER BWC MEMORY ARRAY SENSE AMPS OUTPUT REGISTERS OUTPUT BUFFERS E DQs BWB BWA BWE GW CE1 CE2 CE3 OE ENABLE REGISTER PIPELINED ENABLE INPUT REGISTERS ZZ SLEEP CONTROL Note: 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05666 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised July 5, 2006 [+] Feedback CY7C1215H Selection Guide www.DataSheet4U.com 166 MHz Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 3.5 240 40 133 MHz 4.0 225 40 Unit ns mA mA Pin Configuration 100-Pin TQFP Top View A A CE1 CE2 BWD BWC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A NC DQC DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 BYTE C BYTE D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1215H 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA NC BYTE B BYTE A NC/72M NC/36M VSS VDD Document #: 38-05666 Rev. *B NC/18M NC/9M A A A A A NC/2M NC/4M MODE A A A A A1 A0 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Page 2 of 15 [+] Feedback CY7C1215H Pin Definitions www.DataSheet4U.com Name A0, A1, A I/O InputSynchronous InputSynchronous InputSynchronous InputSynchronous InputClock InputSynchronous InputSynchronous InputSynchronous Description Address Inputs used to select one of the 32K address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1, A0 feed the 2-bit counter. Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes to the SRAM. Sampled on the rising edge of CLK. Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global Write is conducted (ALL bytes are written, regardless of the values on BW[A:D] and BWE). Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampl.


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