PLL521-23

PLL521-23 www.DataSheet4U.com Low Phase Noise PECL VCXO (100MHz to 200MHz) DIE CONFIGURATION 57.5 mil FEATURES 100MHz to 200MHz Fundamental Mode Crystal. Output range: 100MHz – 200MHz. Complementary PECL outputs. Selectable OE Logic (enable high or enable low). Integrated variable capacitors. High pull linearity: < 5%. +/- 120 ppm pull range Supports 2.5V or 3.3V-Power Supply. Available in 16-pinTSSOP and die form. Thickness 10 mil. BUFZSEL VDDOSC OSCOFF OESEL V GNDOSC VCON XIN 18 17 16 15 14 N/C (1460,1435) 13 12 VDDANA VDDBUF VDDBUF PECLBAR PECL GNDBUF 19 11 20 10 9 8 56.5 mil XOUT OECTRL 21 Die ID: 560A-EEEE-ER 7 22 1 2 3 4 5 6 GNDANA (0,0) DESCRIPTION PLL521-23 is a VCXO IC specifically designed to pull high frequency fundamental crystals. Its internal varicaps allow an on chip frequency pulling, controlled by the VCON input. The chip provides a low phase noise, low jitter PECL differential clock output. X PACKAGE CONFIGURATION OUTPUT ENABLE LOGIC SELECTION OESEL* (Pad/Pin #14) 0 (Default) 1 OECTRL* (Pad #22, Pin # 6) 0 (Default) 1 0 1 (Default) State Output enabled Tri-state Tri-state Output enabled BLOCK DIAGRAM OE VCON Oscillator X+ XQ Q Amplifier w/ integrated varicaps * Bond to GND to set to “0”, bond to VDD to set to “1”. No connection results to “default” setting through internal pull-up/-down. Pad #22, Pin #6: Logical states defined by PECL V I H and V I L levels. HIGH IMPEDANCE BUFFER LOGIC SELECTION BUFZSEL (Pad...