PLL520-40

PLL520-40 www.DataSheet4U.com CMOS Low Phase Noise VCXO (for 65-130MHz Fund Xtal) DIE CONFIGURATION 65 mil FEATURES 65MHz to 130MHz Fundamental Mode Crystal. Output range: 65MHz – 130MHz (no PLL). Low Injection Power for crystal 50uW. CMOS outputs (High Drive (30mA) or Standard Drive (10mA) output). Integrated variable capacitors. Supports 2.5V or 3.3V-Power Supply. Available in die form. Thickness 10 mil. DRIVE_SEL^ Reserved VDD VDD VDD VDD N/C N/C (1550,1475) 17 16 25 24 23 22 21 20 19 18 GNDBUF CMOS N/C N/C VDDBUF VDDBUF CMOS N/C N/C XIN XOUT N/C 62 mil 26 27 Die ID: A1313-13C 15 28 14 DESCRIPTION The PLL520-40 is a VCXO IC specifically designed to pull frequency fundamental crystals from 65MHz to 130MHz, with CMOS outputs. Its design was optimized to tolerate higher limits of interelectrode capacitance and bonding capacitance to improve yield. It achieves very low current into the crystal resulting in better overall stability. Its internal varicaps allow an on chip frequency pulling, controlled by the VCON input. 13 N/C OE CTRL^ VCON 29 12 11 30 C502A 31 1 2 3 4 5 6 7 8 10 9 GND Reserved Y (0,0) X Note: ^ denotes internal pull up DIE SPECIFICATIONS Name Value 62 x 65 mil GND 80 micron x 80 micron 10 mil BLOCK DIAGRAM OE VCON Oscillator XIN XOUT Amplifier w/ integrated varicaps Size Reverse side Pad dimensions Thickness DRIVE_SEL AND OE_CTRL TABLE Q DRIVE_SEL (Pad #19) 0 1 OE_CTRL (Pad #30) 0 1 Output Drive High...