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PLL520-18 Dataheets PDF



Part Number PLL520-18
Manufacturers PhaseLink Corporation
Logo PhaseLink Corporation
Description (PLL520-1x) Low Phase Noise VCXO
Datasheet PLL520-18 DatasheetPLL520-18 Datasheet (PDF)

PLL520-17/-18/-19 www.DataSheet4U.com Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal) PIN CONFIGURATION FEATURES • • • • • • • 65MHz to 130MHz Fundamental Mode Crystal. Output range: 65MHz – 800MHz (selectable 1x, 2x, 4x and 8x multipliers). Low Injection Power for crystal 50uW. Available outputs: PECL, LVDS, or CMOS. Integrated variable capacitors. Supports 3.3V-Power Supply. Available in 16 pin (TSSOP or SOIC) VDD XIN XOUT SEL3^ SEL2^ OE VCON GND 1 2 3 4 5 6 7 8 16 15 14 1.

  PLL520-18   PLL520-18


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PLL520-17/-18/-19 www.DataSheet4U.com Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal) PIN CONFIGURATION FEATURES • • • • • • • 65MHz to 130MHz Fundamental Mode Crystal. Output range: 65MHz – 800MHz (selectable 1x, 2x, 4x and 8x multipliers). Low Injection Power for crystal 50uW. Available outputs: PECL, LVDS, or CMOS. Integrated variable capacitors. Supports 3.3V-Power Supply. Available in 16 pin (TSSOP or SOIC) VDD XIN XOUT SEL3^ SEL2^ OE VCON GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SEL0^ SEL1^ GND CLKC VDD CLKT GND GND PLL 520-1x DESCRIPTION The PLL520-17/-18/-19 family of VCXO IC’s is specifically designed to pull high frequency fundamental crystals. They achieve very low current into the crystal resulting in better overall stability. Their internal varicaps allow an on chip frequency pulling, controlled by the VCON input. ^: Internal pull-up OUTPUT ENABLE LOGICAL LEVELS Part # PLL520-18 PLL520-17 PLL520-19 OE 0 (Default) 1 0 1 (Default) State Output enabled Tri-state Tri-state Output enabled BLOCK DIAGRAM OE input: Logical states defined by PECL levels for PLL520-18 Logical states defined by CMOS levels for PLL520-17/-19 SEL OE VCON XIN XOUT Oscillator Amplifier w/ integrated varicaps PLL (Phase Locked Loop) Q Q PLL by-pass PLL520-17/-18/-19 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 1 PLL520-17/-18/-19 www.DataSheet4U.com Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal) PIN DESCRIPTIONS Name XIN XOUT OE VCON GND CLKT CLKC SEL VDD Number 2 3 6 7 8,9, 10, 14 11 13 4,5,15,16 1, 12 Type I I I I P O O I P Description Crystal input. See Crystal Specification on page 3. Crystal output. See Crystal Specification on page 3. Output enable. See Output Enable Logic Levels on page 1. Voltage control input. Ground. True output PECL (PLL520-18) or LVDS (PLL520-19). No Connect for CMOS (PLL520-17). Complementary output PECL (PLL520-18) or LVDS (PLL520-19). CMOS output for (PLL520-17). Multiplier selector pins. These pins have an internal pull-up that will default SEL to ‘1’ when not connected to GND. +3.3V power supply. FREQUENCY SELECTION TABLE Pin #4 SEL3 Pin #5 SEL2 Pin #15 SEL1 Pin #16 SEL0 Selected Multiplier 0 1 1 1 0 0 1 1 1 1 1 1 1 1 0 1 Fin x 8 Fin x 4 Fin x 2 No multiplication All pins have internal pull-ups (default value is 1). Connect to GND to set to 0. ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model SYMBOL V DD VI VO TS TA TJ MIN. -0.5 -0.5 -65 -40 MAX. 4.6 V DD +0.5 V DD +0.5 150 85 125 260 2 UNITS V V V °C °C °C °C kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note : Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 2 PLL520-17/-18/-19 www.DataSheet4U.com Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal) 2. Crystal Specifications PARAMETERS Built-in Capacitance Inter-electrode capacitance C0/C1 ratio (gamma) Oscillation Frequency SYMBOL CX+ CXC0 γ OF CONDITIONS 65MHz to 130MHz (VDD=3.3V) MIN. MAX. 2 2 2 300 200 UNITS pF MHz Fund. 120 3. Voltage Control Crystal Oscillator PARAMETERS VCXO Stabilization Time * VCXO Tuning Range CLK output pullability On-chip Varicaps control range Linearity VCXO Tuning Characteristic VCON input impedance VCON modulation BW SYMBOL T VCXOSTB CONDITIONS From power valid F XIN = 100 – 200MHz; XTAL C 0 /C 1 < 250 0V ≤ VCON ≤ 3.3V VCON=1.65V, ± 1.65V VCON = 0 to 3.3V MIN. TYP. MAX. 10 UNITS ms ppm ppm pF % ppm/V kΩ kHz 200* ± 100* 4 – 18* 10* 65 60 0V ≤ VCON ≤ 3.3V, -3dB 25 Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. 4. General Electrical Specifications PARAMETERS Supply Current (Loaded Outputs) Operating Voltage Output Clock Duty Cycle Short Circuit Current SYMBOL I DD V DD CONDITIONS PECL/LVDS/CMOS @ 1.4V (CMOS) @ 1.25V (LVDS) @ Vdd – 1.3V (PECL) MIN. TYP. MAX. 100/80/40 UNITS mA V % mA 2.97 45 45 45 50 50 50 ± 50 3.63 55 55 55 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 3 PLL520-17/-18/-19 www.DataSheet4U.com Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal) 5. Jitter Sp.


PLL520-17 PLL520-18 PLL520-19


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