CMOS Microcontroller
S3CI9E0X01
www.DataSheet4U.com
FLASH INTERFACE DEVICE
S3CI9E0X01 SPECIFICATION
Version : Ver. 1.0 Date : Jul. 16. 200...
Description
S3CI9E0X01
www.DataSheet4U.com
FLASH INTERFACE DEVICE
S3CI9E0X01 SPECIFICATION
Version : Ver. 1.0 Date : Jul. 16. 2003
Samsung Electronics Co., LTD
Semiconductor Flash Memory Product Planning & Applications
SAMSUNG ELECTRONICS
1
S3CI9E0X01
www.DataSheet4U.com
FLASH INTERFACE DEVICE
Revision History
Revision No. 0.0 Initial Draft History Draft Date Jan. 24 2002 0.1 1.On page 18, BSC is moved from bufferRAM Write Protection command register to system configuration register and bufferRAM Write Protection command register is removed. 2. Host Interface & NAND Flash Interface (page 3) : 1.8V 0.2 --> 1.8V / 2.5V / 3.0V Mar. 13 2002
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Remark
Preliminary
Jan. 25 2002
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Preliminary
1. Package information is added. 2. Some description is updated. 3. Controller ID register default value is modified. (Page 14) 4. Write Protection NAND Flash commands are changed, and description are updated.(Page 23, 56)
Preliminary
0.3
1. Package pin configuration is changed.(page9) 2. Software algorithm of detecting NAND Flash type is added. (page 18, 58) - CE2Ena : 11 bit of system configuration register is changed from ‘reserved’ to ‘CE2Ena’.
Apr. 15 2002
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Preliminary
0.4
1. Minimum latency at sync. Read is changed from 2clocks to 3clocks 2. Technical notes are added - Write Protection truth table is updated(page 58) - Write Protection guidance is updated(page 58) - Internal register reset case is updated(page 61) - Pin connection guidance between Host and Eagle (page 61) ...
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