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STK28N3LLH5
N-channel 30 V, 0.0035 Ω , 28 A, PolarPAK® STripFET™V Power MOSFET
Preliminary Data
Features
Type STK28N3LLH5
■ ■ ■ ■ ■ ■ ■ ■
VDSS 30 V
RDS(on) max < 0.0045 Ω
RDS(on)*Qg 68.4 nC*mΩ
Ultra low top and bottom junction to case thermal resistance RDS(on) * Qg industry benchmark Extremely low on-resistance RDS(on) Very low switching gate charge Fully encapsulated die 100% matte tin finish (in compliance with the 2002/95/EC european directive) High avalanche ruggedness PolarPAK® is a trademark of VISHAY Figure 1. Internal schematic diagram
PolarPAK®
Application
■
Switching applications
Description
This product utilizes the 5th generation of design rules of ST’s proprietary STripFET™ technology. The lowest available RDS(on)*Qg, in this chip scale package, makes this device suitable for the most demanding DC-DC converter applications, where high power density is to be achieved. Table 1. Device summary
Order code STK28N3LLH5 Marking 283L5 Package PolarPAK® Packaging Tape and reel
Bottom View
Top View
September 2008
Rev 2
1/13
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Contents
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STK28N3LLH5
Contents
1 2 3 4 5
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Test circuit ............................................... 6
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
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STK28N3LLH5
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Electrical ratings
1
Electrical ratings
Absolute maximum ratings
Parameter Drain-source voltage (VGS = 0) Gate-source voltage Drain current (continuous) at TC = 25°C Drain current (continuous) at TC = 100°C Drain current (pulsed) Total dissipation at TC = 25°C Derating factor EAS (3) Tj Tstg Single pulse avalanche energy Operating junction temperature Storage temperature Value 30 ± 22 28 17.5 112 5.2 0.0416 1 -55 to 150 Unit V V A A A W W/°C J °C
Table 2.
Symbol VDS VGS ID (1) ID IDM (2) PTOT (1)
1. When mounted on FR-4 board of 1inch2, 2 oz Cu and ≤10sec 2. Pulse width limited by package 3. Starting TJ = 25°C, ID = 10A, VDD = 25V
Table 3.
Symbol
Thermal data
Parameter Typ. 20 1 2.8 Max. 24 1.2 3.4 Unit °C/W °C/W °C/W
Rthj-amb(1) Thermal resistance junction-amb Rthj-c(2) Rthj-c(3) Thermal resistance junction-case (top drain) Thermal resistance junction-case (source)
1. When mounted on FR-4 board of 1inch2, 2 oz Cu and ≤10sec 2. Steady state 3. Measured at source pin when the device is mounted on FR-4 board in steady state
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Electrical characteristics
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STK28N3LLH5
2
Electrical characteristics
(TCASE=25°C unless otherwise specified) Table 4.
Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on)
On/off states
Parameter Drain-source breakdown voltage Zero gate voltage drain current (VGS = 0) Gate body leakage current (VDS = 0) Gate threshold voltage Static drain-source on resistance Test conditions ID = 250 µA, VGS= 0 VDS = Max rating, VDS = Max rating,Tc=125°C VGS = ± 22 V VDS= VGS, ID = 250 µA VGS= 10 V, ID= 14 A VGS= 4.5 V, ID= 14 A 1 Min. 30 1 10
±100
Typ.
Max.
Unit V µA µA nA V Ω Ω
2.5 0.0035 0.0045 0.0047 0.0055
Table 5.
Symbol Ciss Coss Crss Qg Qgs Qgd Qgs1 Qgs2
Dynamic
Parameter Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate-source charge Gate-drain charge Pre Vth gate-to-source charge Post Vth gate-to-source charge Gate input resistance Test conditions Min. Typ. 2300 450 61 19 TBD TBD TBD TBD Max. Unit pF pF pF nC nC nC nC nC
VDS =25 V, f=1 MHz, VGS=0
VDD=15 V, ID = 28 A VGS =4.5 V (see Figure 3) VDD=15 V, ID = 28 A VGS =4.5 V (see Figure 8) f=1 MHz Gate DC Bias = 0 Test signal level = 20 mV open drain
RG
TBD
Ω
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STK28N3LLH5
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Electrical characteristics
Table 6.
Symbol td(on) tr td(off) tf
Switching times
Parameter Turn-on delay time Rise time Test conditions VDD= 15 V, ID= 14 A, RG=4.7 Ω, VGS=4.5 V (see Figure 2) VDD=15 V, ID= 14 A, RG=4.7 Ω, VGS=4.5 V (see Figure 2) Min. Typ. TBD TBD Max. Unit ns ns
Turn-off delay time Fall time
TBD TBD
ns ns
Table 7.
Symbol ISD ISDM(1) VSD(2) trr Qrr IRRM
Source drain diode
Parameter Source-drain current Source-drain current (pulsed) Forward on Voltage Reverse recovery time Reverse recovery charge Reverse recovery current ISD= 25 A, VGS=0 ISD= 25 A, di/dt = 100 A/µs, VDD=20 V, Tj=150°C (see Figure 7) TBD TBD TBD Test conditions Min. Typ. Max. 28 112 1.1 Unit A A V ns nC A
1. Pulse width limited by package 2. Pulsed: pulse duration = 300µs, duty cycle 1.5%
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Test circuits
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STK28N3LLH5
3
Test circuits
Figure 3. Gate charge test circuit
Figure 2.
Sw.