CY7C335

1CY 7C33 5 fax id: 6018 CY7C335 www.DataSheet4U.com Universal Synchronous EPLD Features 100-MHz output registered operation Twelve I/O macrocells, each having: — Registered, three-state I/O pins — Input and output register clock select multiplexer — Feed back multiplexer — Output enable (OE) multiplexer Bypass on input and output registers All twelve macrocell state registers can be hidden User configurable I/O macrocells to implement JK or RS flip-flops and T or D registers Input multiplexer per pair of I/O macrocells allows I/O pin associated with a hidden macrocell state register to be saved for use as an input Four dedicated hidden registers Twelve dedicated registered inputs with individually programmable bypass option Three separate clocks—two input clocks, two output clocks Common (pin 14-controlled) or product term-controlled output enable for each I/O pin 256 product terms—32 per pair of macrocells, variable distribution Global, synchronous, product term-controlled, state register set and reset—inputs to product term are clocked by input clock — 2-ns input set-up and 9-ns output register clock to output — 10-ns input register clock to state register clock 28-pin, 300-mil DIP, LCC, PLCC Erasable and reprogrammable Programmable security bit Functional Description The CY7C335 is a high-performance, erasable, programmable logic device (EPLD) whose architecture has been optimized to enable the user to easily and efficiently construct very...