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AT73C237 Dataheets PDF



Part Number AT73C237
Manufacturers ATMEL Corporation
Logo ATMEL Corporation
Description Power Management and Analog Companions
Datasheet AT73C237 DatasheetAT73C237 Datasheet (PDF)

Features www.DataSheet4U.com • LDO1: 2.75V (Default) and 1.8V (Programmable by TWI), 70 mA Linear Very Low Drop Out Regulator with High PSRR and Low Noise. • LDO2: 1.8V (Default) and 1.5V (Programmable by TWI), 70 mA Linear Low Drop Out Regulator with High PSRR and Low Noise. • LDO3: 1.8V (Default) and 1.5V or 1.2V (Programmable by TWI), 70 mA Linear Low Drop Out Regulator with high PSRR and Low noise. • LDO4: 1.8V, 2mA Linear Low Drop Out Regulator with Very Low Quiescent Current, +/100 mV .

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Features www.DataSheet4U.com • LDO1: 2.75V (Default) and 1.8V (Programmable by TWI), 70 mA Linear Very Low Drop Out Regulator with High PSRR and Low Noise. • LDO2: 1.8V (Default) and 1.5V (Programmable by TWI), 70 mA Linear Low Drop Out Regulator with High PSRR and Low Noise. • LDO3: 1.8V (Default) and 1.5V or 1.2V (Programmable by TWI), 70 mA Linear Low Drop Out Regulator with high PSRR and Low noise. • LDO4: 1.8V, 2mA Linear Low Drop Out Regulator with Very Low Quiescent Current, +/100 mV Adjustable. Main Supply Rail from 2.8V to 5.5V Independent Auxiliary Supply for LDO4 Backup Section, 2.8V to 5.5V Internal State Machine for Startup and Delayed Reset Generation Additional External Reset Input Two Wire Interface for Independent Power Up/Power Down and Output Voltage Programming for Each LDO. • LDOs Voltage Customization Possible on Request • Available in 3 x 3 x 0.9 mm 16-pin QFN Package • Applications: GPS Modules, WLAN Devices, Wireless Modules. • • • • • Power Management and Analog Companions (PMAAC) AT73C237 4-channel Power Management for Wireless Modules 1. Description The AT73C237 is a four-channel Power Supply Power Management Unit (PMU) available in a small outline QFN 3 x 3mm package. It is a fully integrated, attractively priced, combined Power Management device for wireless modules, GPS and WLAN devices. It integrates 4X Linear Low Drop Out Regulators, three of which (LDO1, 2, 3) provide high-accuracy RF performance and 1X (LDO4) with very low quiescent current, that can be supplied by an external backup battery (VDD4) on a separate rail. An internal Low Power Bandgap (LPBG) requiring no external capacitor for decoupling, is used as reference voltage for LDO4 and starts when VDD4 is present. LDO4 regulates its output voltage with extremely low quiescent current, maximizing the lifetime of the backup battery. An Internal State Machine manages the startup of the other LDOs. An economic High Precision Bandgap (HPBG) provides highly accurate, low noise voltage reference to LDOs 1, 2, 3 while operating in switching mode to optimize the quiescent current. The AT73C237 features a Two-wire Interface (TWI) to increase the efficiency of the system by disabling individually each LDO when not needed. 6362A–PMAAC–01-Jul-08 2. Block Diagram www.DataSheet4U.com Figure 2-1. AT73C237 Functional Block Diagram VDD1 (13) LDO1 2.75V/70mA VO1 (14) VDD2 (9) LDO2 1.80V/70mA VO2 (10) VDD3 (3) LDO3 1.80V/70mA VO3 (2) 2.70V Supply Monitor VDD4 (7) LDO4 1.80V/2mA TRIM Low Power Bandgap Reference LPBG RCOSC POR Main Bandgap Reference HVBG VO4 (5) VZAP (8) LDO VBG (16) GNDA (15) XRESIN (1) XRESO (4) TWCK (11) TWD (12) GNDD (6) Level Shifters TWI Interface and Digital State Machine 2 AT73C237 6362A–PMAAC–01-Jul-08 AT73C237 3. Pin Description www.DataSheet4U.com Table 3-1. Pin Name XRESIN VO3 VDD3 XRESO VO4 GNDD VDD4 VZAP (1) Pin Description I/O Input Output Input Output Output GND Input Input Input Output Input Input Input Output GND/Input Output Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Type Digital Analog Power Digital Analog Power Power Digital Power Analog Digital Digital Power Analog Analog Analog Function Reset in pin LDO3 output voltage LDO3 input voltage Reset out pin LDO4 output voltage Digital ground LDO4 input voltage Reserved for manufacturing purposes. LDO2 input voltage LDO2 output voltage TWI input clock or LDO1,2,3 enable at logic “1“, disable at “0“ TWI input/output or tied to Vdd LDO1 input voltage LDO1 output voltage Analog ground and ESD ground Voltage reference for analog cells VDD2 VO2 TWCK(2) TWD(3) VDD1 VO1 GNDA/AVSS VBG Note: (4) 1. Connect to ground (via an internal pull-down) 2. Connected to VDD1, 2 or 3 on AT73C237. 3. Connected to VDD1, 2 or 3 on AT73C237. 4. VDD1, 2, 3 should have the same input voltage. 3 6362A–PMAAC–01-Jul-08 4. Application Block Diagram www.DataSheet4U.com Figure 4-1. AT73C237 Application Block Diagram With GPS Module J1 : "ON" for 237 J2 : "OFF" for 237 C1 TX C5 C9 TWI VBG (16) XRESIN (1) GNDA (15) VO1 (14) VDD1 (13) TWD (12) GPS Baseband Core and IOs VO3 (2) TWCK (11) C3 VDD3 (3) AT73C237 VO2 (10) C7 XRESO (4) VO4 (5) GNDD (6) VDD4 (7) VDD2 (9) VZAP (8) C2 RX C6 C8 C4 D1 D2 3V Back up Coin-Cell Eg: Panasonic CR1025 Li-Ion Battery 3.0V to 4.2V Typical Application Components Design Schematic Reference C1 C2 C3 C4 C5 C6 C7 C8 C9 VBG D1, D2 Pin VO1 VO2 VO3 VO4 VDD1 VDD2 VDD3 VDD4 100 nF ± 15% Ceramic Capacitor, X5R, 0402, 10V MURATA: GRM155R61A104KA01 TDK: C1005X5R1C104KT ON-Semiconductor®: BAS70-04LT1 1 µF ± 15% Ceramic Capacitor, X5R, 0402, 6.3V MURATA: GRM155R60J105KE19 TDK: C1005X5R0J105KT 2.2 µF ± 15% Ceramic Capacitor, X5R, 0402, 6.3V MURATA®: GRM155R60J225ME15 TDK: C1005X5R0J225MT Description 4 AT73C237 6362A–PMAAC–01-Jul-08 AT73C237 5. Electrical Characteristics www.DataSheet4U.com 5.1 Absolute Maximum Ratings Absolute Maximum Ratings *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratin.


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