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LPC2925 Dataheets PDF



Part Number LPC2925
Manufacturers NXP Semiconductors
Logo NXP Semiconductors
Description (LPC2921 - LPC2925) ARM9 microcontroller
Datasheet LPC2925 DatasheetLPC2925 Datasheet (PDF)

D D D R A FT D D R A FT D R A FT R R A FT A FT LPC2921/2923/2925 www.DataSheet4U.com D R A A FT D R A FT D FT D D ARM9 microcontroller with CAN, LIN, and USB device Rev. 00.01 — 24 October 2008 D R Preliminary data sheet D R A A FT FT D R R A FT D R R A FT R A FT R A FT D R FT D R A F R A FT D A 1. General description D The LPC2921/2923/2925 combine an ARM968E-S CPU core with two integrated TCM blocks operating at frequencies of up to 125 MHz, Full-speed USB 2.0 device control.

  LPC2925   LPC2925



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D D D R A FT D D R A FT D R A FT R R A FT A FT LPC2921/2923/2925 www.DataSheet4U.com D R A A FT D R A FT D FT D D ARM9 microcontroller with CAN, LIN, and USB device Rev. 00.01 — 24 October 2008 D R Preliminary data sheet D R A A FT FT D R R A FT D R R A FT R A FT R A FT D R FT D R A F R A FT D A 1. General description D The LPC2921/2923/2925 combine an ARM968E-S CPU core with two integrated TCM blocks operating at frequencies of up to 125 MHz, Full-speed USB 2.0 device controller, CAN and LIN, up to 40 kB SRAM, up to 512 kB flash memory, two 10-bit ADCs, and multiple serial and parallel interfaces in a single chip targeted at consumer, industrial, medical, communication, and automotive markets. To optimize system power consumption, the LPC2921/2923/2925 has a very flexible Clock Generation Unit (CGU) that provides dynamic clock gating and scaling. D R A FT D R A 2. Features „ ARM968E-S processor running at frequencies of up to 125 MHz maximum. „ Multilayer AHB system bus at 125 MHz with four separate layers. „ On-chip memory: ‹ Two Tightly Coupled Memories (TCM), 16 kB Instruction (ITCM) and 16 kB Data TCM (DTCM). ‹ On the LPC2925, two separate internal Static RAM (SRAM) instances, 16 kB each. ‹ On the LPC2923 and LPC2921, one 16 kB SRAM block. ‹ 8 kB ETB SRAM, also usable for code execution and data. ‹ Up to 512 kB high-speed flash-program memory. ‹ 16 kB true EEPROM, byte-erasable/programmable. „ Dual-master, eight-channel GPDMA controller on the AHB multilayer matrix which can be used with both I2C interfaces, the SPI interfaces, and the UARTs, as well as for memory-to-memory transfers including the TCM memories. „ Serial interfaces: ‹ USB 2.0 full-speed device controller with dedicated DMA controller and on-chip device PHY. ‹ Two-channel CAN controller supporting Full-CAN and extensive message filtering. ‹ Two LIN master controllers with full hardware support for LIN communication. The LIN interface can be configured as UART to provide two additional UART interfaces. ‹ Two 550 UARTs with 16-byte Tx and Rx FIFO depths, DMA support, and RS485 (9-bit) support. ‹ Three full-duplex Q-SPIs with four slave-select lines; 16 bits wide; 8 locations deep; Tx FIFO and Rx FIFO. ‹ Two I2C-bus interfaces. D D NXP Semiconductors LPC2921/2923/2925 FT FT FT ARM9 microcontroller with CAN and LIN FT FT FT D D D R R R A A A FT FT www.DataSheet4U.com „ Other peripherals: ‹ Two 10-bit ADCs, 8-channels each, with 3.3 V measurement range provide 8 analog inputs each with conversion times as low as 2.44 μs per channel. Each channel provides a compare function to minimize interrupts. ‹ Multiple trigger-start option for all ADCs: timer, PWM, other ADC and external signal input. ‹ Four 32-bit timers each containing four capture-and-compare registers linked to I/Os. ‹ Four six-channel PWMs (Pulse-Width Modulators) with capture and trap functionality. ‹ Two dedicated 32-bit timers to schedule and synchronize PWM and ADC. ‹ Quadrature encoder int.


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