H5TQ1G83AFP-xxC

H5TQ1G43AFP-xxC H5TQ1G83AFP-xxC H5TQ1G63AFP-xxC www.DataSheet4U.com 1Gb DDR3 SDRAM (Preliminary version) H5TQ1G43AFP-xxC H5TQ1G83AFP-xxC H5TQ1G63AFP-xxC ** Since DDR3 Specification has not been defined completely yet in JEDEC, this document may contain items under discussion. ** Contents may be changed at any time without any notice. Rev. 0.1 / Nov 2007 This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. 1 H5TQ1G43AFP-xxC H5TQ1G83AFP-xxC H5TQ1G63AFP-xxC Revision History Revision No. 0.1 History Preliminary Draft Date 2007-11 Remark www.DataSheet4U.com Rev. 0.1 /Nov 2007 2 H5TQ1G43AFP-xxC H5TQ1G83AFP-xxC H5TQ1G63AFP-xxC Table of Contents 1. Description 1.1 Device Features and Ordering Information 1.1.1 Description 1.1.2 Features www.DataSheet4U.com 1.1.3 Ordering Information 1.1.4 Ordering Frequency 1.2 Package Ballout 1.3 Row and Column Address Table : 512M/1G Fixed 1.4 Pin Functional Description 2. Command Description 2.1 Command Truth Table 2.2 Clock Enable (CKE) Truth Table for Synchronous Transitions 3. Absolute Maximum Ratings 4. Operating Conditions 4.1 Operating Temperature Condition 4.2 DC Operating Conditions 5. AC and DC Input Measurement Levels 5.1 AC and DC Logic Input Levels for Single-Ended Signals 5.2 AC and DC Logic Input Levels for Differential Signals 5.3 Differential Input Cross Point Voltage ...