Document
STB23NM60N-STF23NM60N STI23NM60N-STP23NM60N-STW23NM60N
N-channel 600 V - 0.150 Ω - 19 A - D2PAK - I2PAK - TO-220/FP TO-247, second generation MDmesh™ Power MOSFET
Features
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Type
VDSS (@Tjmax)
RDS(on) max
ID
1
3
3 12
STB23NM60N STI23NM60N STF23NM60N STP23NM60N STW23NM60N
1. Limited only by maximum temperature allowed ■ ■ ■
19 A 19 A 650 V 0.180 Ω 19 A (1)
D²PAK
2 1 3
I²PAK
19 A 19 A
3 1 2
TO-247
3 1 2
100% avalanche tested Low input capacitance and gate charge Low gate input resistance
TO-220
TO-220FP
Figure 1.
Internal schematic diagram
Application
■
Switching applications
Description
This series of devices is designed using the second generation of MDmesh™ technology. This revolutionary Power MOSFET associates a new vertical structure to the company’s strip layout to yield one of the world’s lowest on-resistance and gate charge. It is therefore suitable for the most demanding high efficiency converters.
Table 1.
Device summary
Order codes Marking 23NM60N 23NM60N 23NM60N 23NM60N 23NM60N Package D²PAK I²PAK TO-220FP TO-220 TO-247 Packaging Tape and reel Tube Tube Tube Tube
STB23NM60N STI23NM60N STF23NM60N STP23NM60N STW23NM60N
March 2008
Rev 3
1/19
www.st.com 19
Contents
STB23NM60N-STF/I23NM60N-STP23NM60N-STW23NM60N
Contents
1 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) ............................ 6
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3
Test circuit
................................................ 9
4 5 6
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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STB23NM60N-STF/I23NM60N-STP23NM60N-STW23NM60N
Electrical ratings
1
Electrical ratings
Table 2.
Symbol
Absolute maximum ratings
Value Parameter D²PAK/I²PAK TO-220FP TO-220/TO-247 600 ± 25 19 11.7 76 150 15 --55 to 150 150 2500 19 (1) 11.7 (1) 76 (1) 35 Unit
VDS
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Drain-source voltage (VGS=0) Gate-source voltage Drain current (continuous) at TC = 25 °C Drain current (continuous) at TC = 100 °C Drain current (pulsed) Total dissipation at TC = 25 °C Peak diode recovery voltage slope Insulation withstand voltage (RMS) from all three leads to external heat sink (t = 1 s; TC = 25 °C) Storage temperature Max. operating junction temperature
V V A A A W V/ns V °C °C
VGS ID ID IDM (2) PTOT dv/dt (3) VISO Tstg Tj
1. Limited only by maximum temperature allowed 2. Pulse width limited by safe operating area 3. ISD ≤ 19 A, di/dt ≤400 A/µs, VDD =80% V(BR)DSS
Table 3.
Symbol Rthj-case Rthj-amb Rthj-pcb
Thermal data
Parameter Thermal resistance junction-case max Thermal resistance junction-amb max Thermal resistance junction-pcb max Maximum lead temperature for soldering purposes -62.5 -TO-220 I²PAK TO-247 D²PAK TO-220FP 3.6 50 --30 62.5 -Unit °C/W °C/W °C/W
0.83
Tl
300
°C
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Electrical ratings
STB23NM60N-STF/I23NM60N-STP23NM60N-STW23NM60N
Table 4.
Symbol IAS EAS
Avalanche characteristics
Parameter Avalanche current, repetitive or not-repetitive (pulse width limited by Tj max) Single pulse avalanche energy (starting Tj= 25 °C, ID = IAS, VDD = 50 V) Max value 9 700 Unit A mJ
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STB23NM60N-STF/I23NM60N-STP23NM60N-STW23NM60N
Electrical characteristics
2
Electrical characteristics
(TCASE=25°C unless otherwise specified) Table 5.
Symbol V(BR)DSS
On/off states
Parameter Drain-source breakdown voltage Drain-source voltage slope Zero gate voltage drain current (VGS = 0) Gate body leakage current (VDS = 0) Gate threshold voltage Static drain-source on resistance Test conditions ID = 1 mA, VGS= 0 VDD = 480 V, ID = 19 A, VGS = 10 V VDS = Max rating, VDS = Max rating,@125 °C VGS = ±20 V VDS= VGS, ID = 250 µA VGS= 10 V, ID= 9.5 A 2 3 Min. 600 30 1 100 100 4 Typ. Max. Unit V V/ns µA µA nA V Ω
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dv/dt(1)
IDSS IGSS VGS(th) RDS(on)
1.
0.150 0.180
Characteristic value at turn off on inductive load
Table 6.
Symbol gfs(1) Ciss Coss Crss Coss eq.(2)
Dynamic
Parameter Forward transconductance Input capacitance Output capacitance Reverse transfer capacitance Equivalent output capacitance Gate input resistance Test conditions VDS =15 V, ID= 9.5 A VDS = 50 V, f =1 MHz, VGS = 0 Min. Typ. 17 2050 140 8 260 Max. Unit S pF pF pF pF
VGS = 0, VDS = 0 to 480 V f=1 MHz Gate DC Bias=0 Test signal level=20 mV open drain VDD = 480 V, ID = 19 A VGS = 10 V (see Figure 19)
Rg
4
Ω nC nC nC
Qg Qgs Qgd
1.
Total gate charge Gate-source charge Gate-drain charge
60 10 30
Pulsed: pulse duration = 300 µs, duty cycle 1.5%
2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when V.