AS7C3364PFD36B

February 2005 ® AS7C3364PFD32B AS7C3364PFD36B 3.3V 64K X 32/36 pipeline burst synchronous SRAM Features Organization: 65,536 words × 32 or 36 bits Fast clock speeds to 200 MHz Fast clock to data access: 3.0/3.5/4.0 ns Fast OE access time: 3.0/3.5/4.0 ns Fully synchronous register-to-register operation Double-cycle deselect Asynchronous output enable control Available in 100-pin TQFP package www.DataSheet4U.com Linear or interleaved burst control Individual byte write and global write Snooze mode for reduced power-standby Common data inputs and data outputs Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ Logic block diagram LBO CLK ADV ADSC ADSP A[15:0] 16 CLK CE CLR D CE Address register CLK D Q0 Burst logic Q1 16 Q 14 16 64K × 32/36 Memory array GWE BWE BWd DQd Q Byte write registers CLK D DQc Q Byte write registers CLK D DQb Q Byte write registers CLK D DQa Q Byte write registers CLK D Enable CE register CLK Power down D Enable Q delay register CLK Q 36/32 36/32 BWc BWb BWa CE0 CE1 CE2 4 OE Output registers CLK Input registers CLK ZZ OE 36/32 DQ [a:d] Selection guide –200 Minimum cycle time Maximum clock frequency Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) 5 200 3.0 375 130 30 –166 6 166 3.5 350 100 30 –133 7.5 133 4 325 90 30 Units ns MHz ns mA mA mA 1/31/05; v.1.1 Alliance Semiconductor P. 1...