AS7C33512PFD36A

February 2005 ® AS7C33512PFD32A AS7C33512PFD36A 3.3V 512K × 32/36 pipelined burst synchronous SRAM Features Organization: 524,288 words × 32 or 36 bits Fast clock speeds to 166 MHz Fast clock to data access: 3.4/3.8 ns Fast OE access time: 3.4/3.8 ns Fully synchronous register-to-register operation Double-cycle deselect Asynchronous output enable control Available in 100-pin TQFP package Individual byte write and global write Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ Linear or interleaved burst control Snooze mode for reduced power-standby Common data inputs and data outputs www.DataSheet4U.com Logic block diagram LBO CLK ADV ADSC ADSP A[18:0] 19 CLK CE CLR D CE Address register CLK D Q0 Burst logic Q1 19 Q 17 19 512K × 32/36 Memory array GWE BWE BWd DQd Q Byte write registers CLK D DQc Q Byte write registers CLK D DQb Q Byte write registers CLK D DQa Q Byte write registers CLK D Enable CE register CLK Power down D Enable Q delay register CLK Q 36/32 36/32 BWc BWb BWa CE0 CE1 CE2 4 OE Output registers CLK Input registers CLK ZZ OE 36/32 DQ[a:d] Selection guide Minimum cycle time Maximum clock frequency Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) -166 6 166 3.4 300 90 60 -133 7.5 133 3.8 275 80 60 Units ns MHz ns mA mA mA 2/10/05, v 1.3 Alliance Semiconductor 1 of 19 Copyright © Alliance Semi...