Document
November 2004
®
AS7C33512NTD18A
3.3V 512K × 18 Pipelined burst Synchronous SRAM with NTDTM Features
• Organization: 524,288 words × 18 bits • NTD™ architecture for efficient bus operation • Fast clock speeds to 166 MHz • Fast clock to data access: 3.5/4.0 ns • Fast OE access time: 3.5/4.0 ns • Fully synchronous operation www.DataSheet4U.com • Common data inputs and data outputs • Asynchronous output enable control • Available in100-pin TQFP • Byte write enables • Clock enable for operation hold • Multiple chip enables for easy expansion • 3.3V core power supply • 2.5V or 3.3V I/O operation with separate VDDQ • Self-timed WRITE cycles • “Interleaved” or “Linear burst” modes • Snooze mode for standby operation
Logic block diagram
A[18:0] 19
D
Address register Burst logic
CLK
Q
19
D
CE0 CE1 CE2 R/W BWa BWb ADV/LD LBO ZZ CLK
Write delay addr. registers
CLK
Q
19
Control logic
CLK
Write Buffer
512K x 18 SRAM Array
DQ [a:b]
18
D
Data Q Input Register
CLK
18 18 18
18
CLK CEN CLK
Output
OE Register
18
OE
DQ[a:b]
Selection Guide
-166 Minimum cycle time Maximum clock frequency Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC)
11/30/04; v.2.1
–133 7.5 133 4 400 100 30
Units ns MHz ns mA mA mA
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6 166 3.5 475 130 30
Alliance Semiconductor
Copyright © Alliance Semiconductor. All rights reserved.
AS7C33512NTD18A
®
8 Mb Synchronous SRAM products list1,2
Org 512KX18 256KX32 256KX36 512KX18 256KX32 256KX36 512KX18 www.DataSheet4U.com 256KX32 256KX36 512KX18 256KX32 256KX36 512KX18 256KX32 256KX36 Part Number AS7C33512PFS18A AS7C33256PFS32A AS7C33256PFS36A AS7C33512PFD18A AS7C33256PFD32A AS7C33256PFD36A AS7C33512FT18A AS7C33256FT32A AS7C33256FT36A AS7C33512NTD18A AS7C33256NTD32A AS7C33256NTD36A AS7C33512NTF18A AS7C33256NTF32A AS7C33256NTF36A Mode PL-SCD PL-SCD PL-SCD PL-DCD PL-DCD PL-DCD FT FT FT NTD-PL NTD-PL NTD-PL NTD-FT NTD-FT NTD-FT Speed 166/133 MHz 166/133 MHz 166/133 MHz 166/133 MHz 166/133 MHz 166/133 MHz 7.5/8.5/10 ns 7.5/8.5/10 ns 7.5/8.5/10 ns 166/133 MHz 166/133 MHz 166/133 MHz 7.5/8.5/10 ns 7.5/8.5/10 ns 7.5/8.5/10 ns
1 Core Power Supply: VDD = 3.3V + 0.165V 2 I/O Supply Voltage: VDDQ = 3.3V + 0.165V for 3.3V I/O VDDQ = 2.5V + 0.125V for 2.5V I/O PL-SCD PL-DCD FT NTD1-PL NTD-FT : : : : : Pipelined Burst Synchronous SRAM - Single Cycle Deselect Pipelined Burst Synchronous SRAM - Double Cycle Deselect Flow-through Burst Synchronous SRAM Pipelined Burst Synchronous SRAM with NTDTM Flow-through Burst Synchronous SRAM with NTDTM
1. NTD: No Turnaround Delay. NTDTM is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property of their respective owners. 11/30/04; v.2.1
Alliance Semiconductor
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AS7C33512NTD18A
®
Pin arrangement for TQFP
A A CE0 CE1 NC NC BWb BWa CE2 VDD VSS CLK R/W CEN OE ADV/LD
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A A A
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11/30/04; v..