(AS7C33512FT32A / AS7C33512FT36A) 3.3V 512K x 32/36 Flow-through synchronous SRAM
December 2004
®
AS7C33512FT32A AS7C33512FT36A
3.3V 512K × 32/36 Flow-through synchronous SRAM
Features
• • • • • • • •...
Description
December 2004
®
AS7C33512FT32A AS7C33512FT36A
3.3V 512K × 32/36 Flow-through synchronous SRAM
Features
Organization: 524,288 words × 32 or 36 bits Fast clock to data access: 7.5/8.5/10 ns Fast OE access time: 3.5/4.0 ns Fully synchronous flow-through operation Asynchronous output enable control Available in 100-pin TQFP packages Individual byte write and global write Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ Linear or interleaved burst control Snooze mode for reduced power-standby Common data inputs and data outputs
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Logic block diagram
LBO CLK ADV ADSC ADSP A[18:0] 19 Q0 Burst logic Q1 19 D Q CE Address register CLK D DQd Q Byte write registers CLK D DQ Q c Byte write registers CLK D DQb Q Byte write registers CLK D DQa Q Byte write registers CLK D Enable CE register CLK Power down D Enable Q delay register CLK 36/32 DQ[a:d] Q 4 CLK CE CLR
17
19
512K × 32/36 Memory array
GWE BWE BWd
36/32
36/32
BWc
BWb
BWa CE0 CE1 CE2
OE Output buffer
Input registers CLK
ZZ
OE
Selection guide
Minimum cycle time Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC)
-75 8.5 7.5 275 90 60
-85 10 8.5 250 80 60
-10 12 10 230 80 60
Units ns ns mA mA mA
12/23/04, v 1.4
Alliance Semiconductor
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AS7C33512FT32A AS7C33512FT36A
®
16 Mb Synchronous S...
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