AS7C332MNTD18A

December 2004 ® AS7C332MNTD18A 3.3V 2M × 18 Pipelined SRAM with NTDTM Features Organization: 2,097,152 words × 18 bits NTD™ architecture for efficient bus operation Fast clock speeds to 200 MHz Fast clock to data access: 3.2/3.5/3.8 ns Fast OE access time: 3.2/3.5/3.8 ns Fully synchronous operation Common data inputs and data outputs www.DataSheet4U.com Asynchronous output enable control Available in 100-pin TQFP package Logic block diagram A[20:0] 21 D Byte write enables Clock enable for operation hold Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ Self-timed write cycles Interleaved or linear burst modes Snooze mode for standby operation Address register Burst logic Q 21 CLK CE0 CE1 CE2 R/W BWa BWb ADV / LD LBO ZZ CLK D Q 21 Write delay addr. registers CLK Control logic CLK Write Buffer 2 M x 18 SRAM Array DQ[a,b] 18 D Data Q Input Register CLK 18 18 18 18 CLK CEN CLK OE Output Register 18 OE DQ[a,b] Selection guide -200 Minimum cycle time Maximum clock frequency Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) 12/23/04, V 1.6 -166 6 166 3.5 400 150 90 -133 7.5 133 3.8 350 140 90 Units ns MHz ns mA mA mA P. 1 of 18 5 200 3.2 450 170 90 Alliance Semiconductor Copyright © Alliance Semiconductor. All rights reserved. AS7C332MNTD18A ® 32 Mb Synchronous SRAM products list1,2 Org 2MX18 1MX32 1...