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AS7C33256PFS18B Dataheets PDF



Part Number AS7C33256PFS18B
Manufacturers Alliance Semiconductor Corporation
Logo Alliance Semiconductor Corporation
Description 3.3V 256K X 18 pipeline burst synchronous SRAM
Datasheet AS7C33256PFS18B DatasheetAS7C33256PFS18B Datasheet (PDF)

December 2004 ® AS7C33256PFS18B 3.3V 256K × 18 pipeline burst synchronous SRAM Features • • • • • • • • Organization: 262,144 words × 18 bits Fast clock speeds to 200 MHz Fast clock to data access: 3.0/3.5/4.0 ns Fast OE access time: 3.0/3.5/4.0 ns Fully synchronous register-to-register operation Single-cycle deselect Asynchronous output enable control Available in 100-pin TQFP package • • • • • • • Individual byte write and global write Multiple chip enables for easy expansion Linear or inter.

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December 2004 ® AS7C33256PFS18B 3.3V 256K × 18 pipeline burst synchronous SRAM Features • • • • • • • • Organization: 262,144 words × 18 bits Fast clock speeds to 200 MHz Fast clock to data access: 3.0/3.5/4.0 ns Fast OE access time: 3.0/3.5/4.0 ns Fully synchronous register-to-register operation Single-cycle deselect Asynchronous output enable control Available in 100-pin TQFP package • • • • • • • Individual byte write and global write Multiple chip enables for easy expansion Linear or interleaved burst control Snooze mode for reduced power-standby Common data inputs and data outputs 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ www.DataSheet4U.com Logic block diagram LBO CLK ADV ADSC ADSP A[17:0] CLK CS CLR Burst logic 18 16 18 18 18 Q D CS Address register CLK 256K × 18 Memory array 18 GWE BWb BWE BWa CE0 CE1 CE2 D DQb Q CLK D DQa Q CLK D Byte Write registers Byte Write registers Enable register Q OE 2 Input registers CLK CE CLK ZZ Output registers CLK Power down D Enable Q delay register CLK OE 18 DQ [a,b] Selection guide –200 Minimum cycle time Maximum clock frequency Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) 5 200 3.0 375 130 30 –166 6 166 3.5 350 100 30 –133 7.5 133 4 325 90 30 Units ns MHz ns mA mA mA 12/10/04; v.1.7 Alliance Semiconductor P. 1 of 19 Copyright © Alliance Semiconductor. All rights reserved. AS7C33256PFS18B ® 4 Mb Synchronous SRAM products list1,2 Org 256KX18 128KX32 128KX36 256KX18 128KX32 128KX36 256KX18 www.DataSheet4U.com 128KX32 128KX36 256KX18 128KX32 128KX36 256KX18 128KX32 128KX36 Part Number AS7C33256PFS18B AS7C33128PFS32B AS7C33128PFS36B AS7C33256PFD18B AS7C33128PFD32B AS7C33128PFD36B AS7C33256FT18B AS7C33128FT32B AS7C33128FT36B AS7C33256NTD18B AS7C33128NTD32B AS7C33128NTD36B AS7C33256NTF18B AS7C33128NTF32B AS7C33128NTF36B Mode PL-SCD PL-SCD PL-SCD PL-DCD PL-DCD PL-DCD FT FT FT NTD-PL NTD-PL NTD-PL NTD-FT NTD-FT NTD-FT Speed 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 6.5/7.5/8.0/10 ns 6.5/7.5/8.0/10 ns 6.5/7.5/8.0/10 ns 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 6.5/7.5/8.0/10 ns 6.5/7.5/8.0/10 ns 6.5/7.5/8.0/10 ns 1 Core Power Supply: VDD = 3.3V + 0.165V 2 I/O Supply Voltage: VDDQ = 3.3V + 0.165V for 3.3V I/O VDDQ = 2.5V + 0.125V for 2.5V I/O PL-SCD PL-DCD FT NTD1-PL NTD-FT : : : : : Pipelined Burst Synchronous SRAM - Single Cycle Deselect Pipelined Burst Synchronous SRAM - Double Cycle Deselect Flow-through Burst Synchronous SRAM Pipelined Burst Synchronous SRAM with NTDTM Flow-through Burst Synchronous SRAM with NTDTM 1. NTD: No Turnaround Delay. NTDTM is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property of their respective owners. 12/10/04; v.1.7 Alliance Semiconductor P. 2 of 19 AS7C33256PFS18B ® Pin arrangement 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 8.



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