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AS7C33128FT18B Dataheets PDF



Part Number AS7C33128FT18B
Manufacturers Alliance Semiconductor Corporation
Logo Alliance Semiconductor Corporation
Description 3.3V 128K x 18 Flow Through Synchronous SRAM
Datasheet AS7C33128FT18B DatasheetAS7C33128FT18B Datasheet (PDF)

December 2004 ® AS7C33128FT18B 3.3V 128K × 18 Flow Through Synchronous SRAM Features • • • • • • • • Organization: 131,072 words × 18 bits Fast clock to data access: 6.5/7.5/8.0/10.0 ns Fast OE access time: 3.5/4.0 ns Fully synchronous flow through operation Asynchronous output enable control Economical 100-pin TQFP package Individual byte write and Global write Multiple chip enables for easy expansion • • • • • 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ Linear or int.

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December 2004 ® AS7C33128FT18B 3.3V 128K × 18 Flow Through Synchronous SRAM Features • • • • • • • • Organization: 131,072 words × 18 bits Fast clock to data access: 6.5/7.5/8.0/10.0 ns Fast OE access time: 3.5/4.0 ns Fully synchronous flow through operation Asynchronous output enable control Economical 100-pin TQFP package Individual byte write and Global write Multiple chip enables for easy expansion • • • • • 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ Linear or interleaved burst control Snooze mode for reduced power standby Common data inputs and data outputs www.DataSheet4U.com Logic block diagram LBO CLK ADV ADSC ADSP A[16:0] CLK CS CLR Burst logic 2 2 17 Q D CS Address register CLK 128K × 18 Memory array 17 18 18 17 15 GWE BWb BWE BWa CE0 CE1 CE2 D DQb Q Byte Write registers CLK D DQa Q Byte Write registers CLK D 2 OE Enable register Q CE CLK Output Buffers Input registers CLK ZZ Power down D Enable Q delay register CLK OE 18 DQ [a,b] Selection guide –65 Minimum cycle time Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) 7.5 6.5 250 120 30 -75 8.5 7.5 225 100 30 -80 10 8.0 200 90 30 -10 12 10.0 175 90 30 Units ns ns mA mA mA 12/10/04; v.1.3 Alliance Semiconductor P. 1 of 19 Copyright © Alliance Semiconductor. All rights reserved. AS7C33128FT18B ® 2 Mb Synchronous SRAM products list1,2 Org 128KX18 64KX32 64KX36 128KX18 64KX32 64KX36 128KX18 www.DataSheet4U.com 64KX32 64KX36 Part Number AS7C33128PFS18B AS7C3364PFS32B AS7C3364PFS36B AS7C33128PFD18B AS7C3364PFD32B AS7C3364PFD36B AS7C33128FT18B AS7C3364FT32B AS7C3364FT36B Mode PL-SCD PL-SCD PL-SCD PL-DCD PL-DCD PL-DCD FT FT FT Speed 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 6.5/7.5/8.0/10 ns 6.5/7.5/8.0/10 ns 6.5/7.5/8.0/10 ns 1 Core Power Supply: VDD = 3.3V + 0.165V 2 I/O Supply Voltage: VDDQ = 3.3V + 0.165V for 3.3V I/O VDDQ = 2.5V + 0.125V for 2.5V I/O PL-SCD PL-DCD FT : : : Pipelined Burst Synchronous SRAM - Single Cycle Deselect Pipelined Burst Synchronous SRAM - Double Cycle Deselect Flow-through Burst Synchronous SRAM 12/10/04; v.1.3 Alliance Semiconductor P. 2 of 19 AS7C33128FT18B ® Pin arrangement 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE0 CE1 NC NC BWb BWa CE2 VDD VSS CLK GWE BWE OE ADSC ADSP ADV A A www.DataSheet4U.com NC NC NC VDDQ VSSQ NC NC DQb0 DQb1 VSSQ VDDQ DQb2 DQb3 NC VDD NC VSS DQb4 DQb5 VDDQ VSSQ DQb6 DQb7 DQpb NC VSSQ VDDQ NC NC NC 12/10/04; v.1.3 LBO A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A NC 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 TQFP 14 × 20mm 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A NC NC VDDQ VSSQ NC DQpa DQa7 DQa6 VSSQ VDDQ DQa5 DQa4 VSS NC VDD ZZ DQa3 DQa2 VDDQ VSSQ DQa1 DQa0 NC NC VSSQ VDDQ NC NC NC Alliance Semiconductor P. 3 of 19 AS7C33128FT18B ® Functional description The AS7C33128FT18B is a high-performance CMOS 2-Mbit synchronous Static Random Access Memory (SRAM) device organized as 131,072 words × 18 bits. Fast cycle times of 7.5/8.5/10/12 ns with clock access times (tCD) of 6.5/7.5/8.0/10 ns. Three chip enable (CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses. Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register when ADSP is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation, the data accessed by the current address registered in the address registers by the positive edge of CLK are carried to the data-out buffer. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on all subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled low and both address strobes are high. Burst mode is selectable with the LBO input. www.DataSheet4U.com With LBO unconnected or driven high, burst operations use an interleaved count sequence. With LBO driven low, the device uses a linear count sequence. Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 18 bits regardless of the state of individual BW[a,b] inputs. Alternately, when GWE is high, one or more bytes may be written by asserting BWE and the appropriate individual byte BWn signals. BWn is ignored on the clock edge that samples ADSP low, but it is sampled on all subsequent clock edges. Output buffers are disabled when BWn is sampled LOW regardless of OE. Data is clocked into the data input register when BWn is sa.


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