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U631H64 Dataheets PDF



Part Number U631H64
Manufacturers Simtek Corporation
Logo Simtek Corporation
Description SoftStore 8K x 8 nvSRAM
Datasheet U631H64 DatasheetU631H64 Datasheet (PDF)

Obsolete - Not Recommended for New Designs U631H64 SoftStore 8K x 8 nvSRAM Features High-performance CMOS nonvolatile static RAM 8192 x 8 bits • 25, 35 and 45 ns Access Times • 12, 20 and 25 ns Output Enable Access Times • Software STORE Initiation (STORE Cycle Time < 10 ms) • Automatic STORE Timing • 105 STORE cycles to EEPROM • 10 years data retention in www.DataSheet4U.com EEPROM • Automatic RECALL on Power Up • Software RECALL Initiation (RECALL Cycle Time < 20 μs) • Unlimited RECALL cycles.

  U631H64   U631H64


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Obsolete - Not Recommended for New Designs U631H64 SoftStore 8K x 8 nvSRAM Features High-performance CMOS nonvolatile static RAM 8192 x 8 bits • 25, 35 and 45 ns Access Times • 12, 20 and 25 ns Output Enable Access Times • Software STORE Initiation (STORE Cycle Time < 10 ms) • Automatic STORE Timing • 105 STORE cycles to EEPROM • 10 years data retention in www.DataSheet4U.com EEPROM • Automatic RECALL on Power Up • Software RECALL Initiation (RECALL Cycle Time < 20 μs) • Unlimited RECALL cycles from EEPROM • Unlimited Read and Write to SRAM • Single 5 V ± 10 % Operation • Operating temperature ranges: 0 to 70 °C -40 to 85 °C • QS 9000 Quality Standard • ESD characterization according MIL STD 883C M3015.7-HBM (classification see IC Code Numbers) • RoHS compliance and Pb- free • Packages: PDIP28 (300 mil) SOP28 (330 mil) Pin Configuration n.c. A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 VCC W n.c. A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 • Description The U631H64 has two separate modes of operation: SRAM mode and nonvolatile mode. In SRAM mode, the memory operates as an ordinary static RAM. In nonvolatile operation, data is transferred in parallel from SRAM to EEPROM or from EEPROM to SRAM. In this mode SRAM functions are disabled. The U631H64 is a fast static RAM (25, 35, 45 ns), with a nonvolatile electrically erasable PROM (EEPROM) element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resides in EEPROM. Data transfers from the SRAM to the EEPROM (the STORE operation), or from the EEPROM to the SRAM (the RECALL operation) are initiated through software sequences. The U631H64 combines the high performance and ease of use of a fast SRAM with nonvolatile data integrity. Once a STORE cycle is initiated, further input or output are disabled until the cycle is completed. Because a sequence of addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence or the sequence will be aborted. Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times. Pin Description Signal Name A0 - A12 DQ0 - DQ7 E G W VCC VSS Signal Description Address Inputs Data In/Out Chip Enable Output Enable Write Enable Power Supply Voltage Ground PDIP 22 SOP 21 20 19 18 17 16 15 Top View March 31, 2006 STK Control #ML0045 1 Rev 1.0 U631H64 Block Diagram A5 Row Decoder A6 A7 A8 A9 A11 A12 DQ0 DQ1 SRAM Array 128 Rows x 64 x 8 Columns Store/ Recall Control EEPROM Array 128 x (64 x 8) STORE RECALL VCC VSS VCC Column I/O Input Buffers Column Decoder Software Detect www.DataSheet4U.com DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 A0 - A12 A0 A1 A2 A3 A4 A10 G E W Truth Table for SRAM Operations Operating Mode Standby/not selected Internal Read Read Write * H or L Characteristics All voltages are referenced to VSS = 0 V (ground). All characteristics are valid in the power supply voltage range and in the operating temperature range specified. Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V, with the exception of the tdis-times and ten-times, in which cases transition is measured ± 200 mV from steady-state voltage. E H L L L W * G * DQ0 - DQ7 High-Z High-Z Data Outputs Low-Z Data Inputs High-Z H H L H L * Absolute Maximum Ratinga Power Supply Voltage Input Voltage Output Voltage Power Dissipation Operating Temperature Storage Temperature C-Type K-Type Symbol VCC VI VO PD Ta Tstg Min. -0.5 -0.3 -0.3 Max. 7 VCC+0.5 VCC+0.5 1 Unit V V V W °C °C °C 0 -40 -65 70 85 150 a: Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. STK Control #ML0045 2 Rev 1.0 March 31, 2006 U631H64 Recommended Operation Conditions Power Supply Voltage Input Low Voltage Input High Voltage Symbol VCC VIL VIH -2 V at Pulse Width 10 ns permitted Conditions Min. 4.5 -0.3 2.2 Max. 5.5 0.8 VCC+0.3 Unit V V V www.DataSheet4U.com C-Type DC Characteristics Operating Supply Currentb Symbol ICC1 VCC VIL VIH tc tc tc Average Supply Current during STOREc ICC2 VCC E W VIL VIH VCC E tc tc tc Average Supply Current at tcR = 200 nsb (Cycling CMOS Input Levels) Standby Supply Currentd (Stable CMOS Input Levels) ICC3 VCC W VIL VIH VCC E VIL VIH Conditions Min. = 5.5 V = 0.8 .


EE2225 U631H64 K4D26323QG


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