Document
R8A66120FFA
4M-bit x 2 MULTIPLE FIELD MEMORY Description
RJJ03FXXXREJ03F0161-0170 Rev.1.70 May.16.2008
R8A66120FFA is high-speed field memory with two FIFO (First In First Out) memories of 4M-bit, which uses high-performance silicon gate process technology.
Features
•Total memory Capacity 8Mega-bit •High speed operation cycle time 10.0ns(Min.) fmax = 100MHz output access time 6.0ns(Max.) •Output hold time 1.0ns(Min.) •Supply voltage 3.3 ± 0.3V •Variable length delay bit •Synchronous write/read operation •3 states output •Package PLQP0048KB-A (48P6Q-A) ( 48pins 7x7mm body LQFP ) W-CDMA base station, Digital PPC, Digital TV,VTR and so on.
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Application Mode Descriptions
1K-word = 1024-words
1024K-word 4bit bus I/F
DA<3:0> CKA WRESA WEA DB<3:0> CKB WRESB WEB
4 1024K-w X 4-bit FIFO 4 1024K-w X 4-bit FIFO
4
QA<3:0> RRESA REA
4
QB<3:0> RRESB REB
The 2 pieces of 1024K-word x 4-bit FIFO can be operated completely independently. 2-system individual input 2-system individual output
Pin Configuration (Top view)
Outline: PLQP0048KB-A (48P6Q-A)
REJ03F0161-0170 Rev.1.70 May.16.2008 page 1 of 14
R8A66120FFA Block Diagram
Data input DA<3:0> DB<3:0>
INPUT BUFFER
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Clock inputs MODE CONTROL CIRCUIT CKA CKB
Mode setting input MODE
WRITE CONTROL CIRCUIT
READ CONTROL CIRCUIT
Write control inputs for A-system WRESA WEA
MEMORY ARRAY 256K-word x 16-bit 256K-word x 16-bit
Read control inputs for A-system RRESA REA
READ ADDRESS COUNTER
WRITE ADDRESS COUNTER
Write control inputs for B-system WRESB WEB
Read control inputs for B-system RRESB REB
Power on reset input POR Test setting input TEST<2:1> MODE CONTROL CIRCUIT
Vcc GND
OUTPUT BUFFER
QA<3:0> Data output
QB<3:0>
REJ03F0161-0170 Rev.1.70 May.16.2008 page 2 of 14
R8A66120FFA
Pin Function Description
Pin name (*1) CKx WEx Name Clock input Write enable input Input/ Output Input Input Number of pin(s) 2 2 Function They are clock inputs. They are write enable control inputs. When they are "L", a write enable status is provided. They are reset inputs to initialize a write address counter of internal FIFO. When they are "L", a write reset status is provided. They are read enable control inputs. When they are "L", a read enable status is provided. They are reset inputs to initialize a read address counter of internal FIFO. When they are "L", a read reset status is provided. They are data input bus. They are data output bus. This is a pin for setting operation mode. MODE should be fixed at "L". They are pins for test. TEST<2:1> should be fixed at "L". This is a power on reset input. They are 3.3 V power supply pins. They are ground pins.
WRESx
Write reset input
Input
2
REx
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Read enable input
Input
2
RRESx
Read reset input
Input
2
Dx<3:0> Qx<3:0> MODE TEST<2:1> POR Vcc GND
Data input Data output Mode setting input Test setting input Power on reset input Power supply pin Ground pin
Input Output Input Input Input -
8 8 1 2 1 9.