Document
KM68257C/CL
Document Title
PRELIMINARY CMOS SRAM
32Kx8 Bit High Speed Static RAM(5V Operating), Evolutionary Pin out. Operated at Commercial Temperature Range.
Revision History
Rev No. Rev. 0.0 Rev. 1.0
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History Initial release with Preliminary. Release to final Data Sheet. 1. Delete Preliminary Update A.C parameters 2.1. Updated A.C parameters Previous spec. Updated spec. Items (12/15/20ns part) (12/15/20ns part) tOE - / 8/10ns - / 7 /9 ns tCW - /12/ - ns - /11/ - ns tHZ 8/10/10ns 6/7/8ns tOHZ - / 8 / - ns - / 7 / - ns tDW - / 9 / - ns - / 8 / - ns 2.2. Add Voh1=3.95V with the test condition as Vcc=5V±5% at 25°C 3.1. Add 28-TSOP1 Package. 3.2. Add L-version. 3.3. Add Data Rentention Characteristics.
Draft Data Apr. 1st, 1994 May 14th,1994
Remark Preliminary Final
Rev. 2.0
Oct. 4th, 1994
Final
Rev. 3.0
Feb. 22th, 1996
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1Rev 3.0 February-1996
KM68257C/CL
32K x 8 Bit High-Speed CMOS Static RAM
FEATURES
Fast Access Time 12, 15, 20§À(Max.) Low Power Dissipation Standby (TTL) : 40§Ì(Max.) (CMOS) : 2§Ì(Max.) 0.1§Ì(Max.)- L-ver. only Operating KM68257C/CL - 12 : 165§Ì(Max.) KM68257C/CL - 15 : 150§Ì(Max.) KM68257C/CL - 20 : 140§Ì(Max.) www.DataSheet4U.com Single 5.0V±10% Power Supply TTL Compatible Inputs and Outputs I/O Compatible with 3.3V Device Fully Static Operation - No Clock or Refresh required Three State Outputs Low Data Retention Voltage : 2V(Min.)- L-ver. only Standard Pin Configuration KM68257C/CLP : 28-DIP-300 KM68257C/CLJ : 28-SOJ-300 KM68257C/CLTG : 28-TSOP1-0813, 4F
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PRELIMINARY CMOS SRAM
GENERAL DESCRIPTION
The KM68257C is a 262,144-bit high-speed Static Random Access Memory organized as 32,768 words by 8 bits. The KM68257C uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using SAMSUNG's advanced CMOS process and designed for high-speed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The KM68257C is packaged in a 300 mil 28-pin plastic DIP, SOJ or TSOP1 forward.
PIN CONFIGURATION(Top View)
OE A11 A9 A8 A13 WE Vcc A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 Vss I/O3 I/O2 I/O1 A0 A1 A2
TSOP1
FUNCTIONAL BLOCK DIAGRAM
Clk Gen. A3 A4 A5 A6 A7 A8 A12 A13 A14 I/O1 ~ I/O8 Pre-Charge-Circuit
A14 1 A12 2
28 Vcc 27 WE 26 A13 25 A8 24 A9 23 A11
Row Select
A7 3
Memory Array 512 Rows 64x8 Columns
A6 4 A5 5 A4 6 A3 7 A2 8 A1 9
SOJ/DIP
22 OE 21 A10 20 CS 19 I/O8 18 I/O7 17 I/O6 16 I/O5 15 I/O4
Data Cont.
I/O Circuit Column Select
A0 10 I/O1 11 I/O2 12
CLK Gen. A0 CS WE OE A1 A2 A9 A10 A11
I/O3 13 Vss 14
PIN FUNCTION
Pin Name A0 - A14 WE CS OE I/O1 ~ I/O8 VCC VSS -2Write Enable Chip Select Output Enable Data Inputs/Outputs Power(+5.0V) Ground Rev 3.0 February-1996 Pin Function Address Inputs
KM68257C/CL
ABSOLUTE MAXIMUM RATINGS*
Parameter Voltage on Any Pin Relative to VSS Voltage on VCC Supply Relative to VSS Power Dissipation Storage Temperature Operating Temperature Symbol VIN, VOUT VCC PD TSTG TA Rating -0.5 to 7.0 -0.5 to 7.0 1.0 -65 to 150 0 to 70
PRELIMINARY CMOS SRAM
Unit V V
W
°C °C
* Stresses greater than those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a stress ra ting only and functional operation of the device at these at these or any other conditions above those indicated in the operating sections of thi s specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. www.DataSheet4U.com
RECOMMENDED DC OPERATING CONDITIONS(TA=0 to 70°C)
Parameter Supply Voltage Ground Input Low Voltage Input Low Voltage
* VIL(Min) = -2.0(Pulse Width ≤10ns) for I ≤20§Ì ** VIH(Max) = V CC+2.0V(Pulse Width ≤10ns) for I ≤20§Ì
Symbol VCC VSS VIH VIL
Min 4.5 0 2.2 -0.5*
Typ 5.0 0 -
Max 5.5 0 VCC+0.5** 0.8
Unit V V V V
DC AND OPERATING CHARACTERISTICS(TA=0 to 70°C,VCC=5.0V±10% unless otherwise specified)
Parameter Input Leakage Current Output Leakage Current Symbol ILI ILO Test Conditions VIN = VSS to VCC CS=VIH or OE=VIH or WE=VIL VOUT = VSS to VCC Min. Cycle, 100% Duty CS=VIL, VIN = VIH or VIL, IOUT=0mA Min. Cycle, CS=VIH f=0MHz, CS≥VCC-0.2V, VIN≥VCC-0.2V or VIN≤0.2V IOL=8mA IOH=-4mA IOH1=0.1mA Normal L-ver 12ns 15ns 20ns Min -2 -2 2.4 Max 2 2 165 150 140 40 2 0.1 0.4 3.95 Unit µA µA
Operating Current
ICC ISB
§Ì §Ì §Ì
V V V
Standby Current Output Low Voltage Level Output High Voltage Level
* VCC=5.0V±5% Temp..