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KM681001B Dataheets PDF



Part Number KM681001B
Manufacturers Samsung semiconductor
Logo Samsung semiconductor
Description 128K x 8 Bit High-Speed CMOS Static RAM
Datasheet KM681001B DatasheetKM681001B Datasheet (PDF)

PRELIMINARY KM681001B Document Title 128Kx8 Bit High Speed Static RAM(5V Operating), Evolutionary Pin out. Operated at Commercial and Industrial Temperature Range. CMOS SRAM Revision History Rev . No. Rev. 0.0 Rev. 1.0 History Initial release with Design Target. Release to Preliminary Data Sheet. 1. Replace Design Target to Preliminary. Release to Final Data Sheet. 1. Delete Preliminary. 2. Delete 17ns, L-version and Industrial Temperature Part. 3. Delete Voh1=3.95V. 4. Delete Data Retention C.

  KM681001B   KM681001B


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PRELIMINARY KM681001B Document Title 128Kx8 Bit High Speed Static RAM(5V Operating), Evolutionary Pin out. Operated at Commercial and Industrial Temperature Range. CMOS SRAM Revision History Rev . No. Rev. 0.0 Rev. 1.0 History Initial release with Design Target. Release to Preliminary Data Sheet. 1. Replace Design Target to Preliminary. Release to Final Data Sheet. 1. Delete Preliminary. 2. Delete 17ns, L-version and Industrial Temperature Part. 3. Delete Voh1=3.95V. 4. Delete Data Retention Characteristics and Wave form. 5. Relex operating current Speed Previous Now 15ns 130mA 125mA 17ns 120mA 20ns 110mA 123mA Draft Data Feb. 1st, 1997 Jun. 1st, 1997 Remark Design Target Preliminary www.DataSheet4U.comRev. 2.0 Feb. 6th. 1998 Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. Rev 2.0 February 1998 -1- PRELIMINARY KM681001B 128K x 8 Bit High-Speed CMOS Static RAM FEATURES • Fast Access Time 15, 20ns(Max.) • Low Power Dissipation Standby (TTL) : 20mA(Max.) (CMOS) : 5mA(Max.) Operating KM681001B - 15 : 125mA(Max.) KM681001B - 20 : 123mA(Max.) • Single 5.0V±10% Power Supply • TTL Compatible Inputs and Outputs • Fully Static Operation - No Clock or Refresh required • Three State Outputs www.DataSheet4U.com • Standard Pin Configuration KM681001BJ : 32-SOJ-400 KM681001BSJ : 32-SOJ-300 CMOS SRAM GENERAL DESCRIPTION The KM681001B is a 1,048,576-bit high-speed Static Random Access Memory organized as 131,072 words by 8 bits. The KM681001B uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using Samsung′s advanced CMOS process and designed for high-speed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The KM681001B is packaged in a 400/300 mil 32-pin plastic SOJ. PIN CONFIGURATION(Top View) N.C A0 A1 1 2 3 4 5 6 7 8 9 10 11 12 32 Vcc 31 A16 30 CS2 29 WE 28 A15 27 A14 26 A13 FUNCTIONAL BLOCK DIAGRAM A2 A3 A4 Clk Gen. A0 A1 A2 A3 A4 A5 A6 A7 A8 Pre-Charge Circuit A5 A6 A7 A8 SOJ 25 A12 24 OE 23 A11 22 CS1 21 I/O8 20 I/O7 19 I/O6 18 I/O5 17 I/O4 Row Select Memory Array 512 Rows 256x8 Columns A9 A10 I/O1 13 I/O2 14 I/O3 15 Vss 16 I/O1 ~ I/O8 Data Cont. CLK Gen. I/O Circuit Column Select A9 A10 A11 A12 A13 A14 A15 A16 CS2 CS1 WE OE PIN FUNCTION Pin Name A0 - A16 WE CS1, CS2 OE I/O1 ~ I/O8 VCC VSS N.C Pin Function Address Inputs Write Enable Chip Selects Output Enable Data Inputs/Outputs Power(+5.0V) Ground No Connection -2- Rev 2.0 February 1998 PRELIMINARY KM681001B ABSOLUTE MAXIMUM RATINGS* Parameter Voltage on Any Pin Relative to VSS Voltage on VCC Supply Relative to VSS Power Dissipation Storage Temperature Operating Temperature Symbol VIN, VOUT VCC PD TSTG TA Rating -0.5 to 7.0 -0.5 to 7.0 1.0 -65 to 150 0 to 70 Unit V V CMOS SRAM W °C °C * Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. www.DataSheet4U.com RECOMMENDED DC OPERATING CONDITIONS(TA=0 to 70°C) Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 4.5 0 2.2 -0.5* Typ 5.0 0 Max 5.5 0 VCC+0.5** 0.8 Unit V V V V NOTE: * VIL(Min) = -2.0V a.c(Pulse Width≤10ns) for I≤20mA ** VIH(Max) = VCC + 2.0V a.c (Pulse Width≤10ns) for I≤20mA DC AND OPERATING CHARACTERISTICS(TA=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified) Parameter Input Leakage Current Output Leakage Current Operating Current Symbol ILI ILO ICC Test Conditions VIN = VSS to VCC CS1=VIH or CS2=VIL or OE=VIH or WE=VIL, VOUT = VSS to VCC Min. Cycle, 100% Duty CS1=VIL, CS2=VIH, VIN=VIH or VIL, IOUT=0mA Min. Cycle, CS1=VIH or CS2=VIL f=0MHz, CS1≥VCC-0.2V or CS2≤0.2V, VIN≥VCC-0.2V or VIN≤0.2V IOL=8mA IOH=-4mA 15ns 20ns Min -2 -2 2.4 Max 2 2 125 123 20 5 0.4 V V mA Unit µA µA mA Standby Current ISB ISB1 Output Low Voltage Level Output High Voltage Level VOL VOH CAPACITANCE*(TA=25°C, f=1.0MHz) Item Input/Output Capacitance Input Capacitance Symbol CI/O CIN Test Conditions VI/O=0V VIN=0V MIN Max 8 6 Unit pF pF * NOTE : Capacitance is sampled and not 100% tested. -3- Rev 2.0 February 1998 PRELIMINARY KM681001B AC CHARACTERISTICS(TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.) TEST CONDITIONS Parameter Input Pulse Levels Input Rise and Fall Times Input and Output timing Reference Levels Output Load.


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