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ICS8344-01 Dataheets PDF



Part Number ICS8344-01
Manufacturers Integrated Circuit Systems
Logo Integrated Circuit Systems
Description 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Datasheet ICS8344-01 DatasheetICS8344-01 Datasheet (PDF)

Integrated Circuit Systems, Inc. ICS8344-01 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER FEATURES • 24 LVCMOS outputs, 7Ω typical output impedance • 2 selectable CLKx, nCLKx inputs • CLK0, nCLK0 and CLK1, nCLK1 pairs can accept the following input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Output frequency up to 250MHz • Translates any single ended input signal to LVCMOS with resistor bias on nCLK input • Synchronous clock enable • Output skew: 200 ps (maximum) • Part-to-part skew: 90.

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Integrated Circuit Systems, Inc. ICS8344-01 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER FEATURES • 24 LVCMOS outputs, 7Ω typical output impedance • 2 selectable CLKx, nCLKx inputs • CLK0, nCLK0 and CLK1, nCLK1 pairs can accept the following input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Output frequency up to 250MHz • Translates any single ended input signal to LVCMOS with resistor bias on nCLK input • Synchronous clock enable • Output skew: 200 ps (maximum) • Part-to-part skew: 900ps (maximum) • Bank skew: 85ps (maximum) • Propagation delay: 5ns (maximum) • 3.3V, 2.5V or mixed 3.3V, 2.5V operating supply modes • 0°C to 70°C ambient operating temperature • Industrial temperature information available upon request GENERAL DESCRIPTION The ICS8344-01 is a low voltage, low skew fanout buffer and a member of the HiPerClockS™ HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8344-01 has two selectable clock inputs. The CLK0, nCLK0 and CLK1, nCLK1 pairs can accept most standard differential input levels. The ICS8344-01 is designed to translate any differential signal levels to LVCMOS levels. The low impedance LVCMOS outputs are designed to drive 50Ω series or parallel terminated www.DataSheet4U.com transmission lines. The effective fanout can be increased to 48 by utilizing the ability of the outputs to drive two series terminated lines. Redundant clock applications can make use of the dual clock input. The dual clock inputs also facilitate board level testing. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. The outputs are driven low when disabled. The ICS8344-01 is characterized at full 3.3V, full 2.5V and mixed 3.3V input and 2.5V output operating supply modes. ,&6 Guaranteed output and part-to-part skew characteristics make the ICS8344-01 ideal for those clock distribution applications demanding well defined performance and repeatability. BLOCK DIAGRAM CLK_SEL CLK0 nCLK0 CLK1 nCLK1 PIN ASSIGNMENT Q8 Q9 VDDO GND Q10 Q11 Q12 Q13 VDDO GND Q14 Q15 1 0 Q0 - Q7 Q16 Q17 VDDO GND Q18 Q19 Q20 Q21 VDDO GND Q22 Q23 Q8 - Q15 Q16 - Q23 LE Q 48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24 ICS8344-01 Q7 Q6 VDDO GND Q5 Q4 Q3 Q2 VDDO GND Q1 Q0 CLK_EN nD nc OE CLK_EN CLK0 nCLK0 VDD GND CLK1 nCLK1 VDD GND CLK_SEL OE 48-Lead LQFP 7mm x 7mm x 1.4mm Y Package Top View 8344AY-01 www.icst.com/products/hiperclocks.html 1 REV. B AUGUST 6, 2001 Integrated Circuit Systems, Inc. ICS8344-01 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER Type Output Power Power Input Power Input Input Input Input Input Input Description Q16 thru Q23 outputs. 7Ω typical output impedance. Output supply pins. Connect 3.3V or 2.5V. Power supply ground. Connect to ground. Clock select input. When HIGH, selects CLK1, nCLK inputs, Pulldown When LOW, selects CLK0, nCLK0 inputs. LVCMOS / LVTTL interface levelss. Positive supply pins. Connect 3.3V or 2.5V. Pullup Pullup Inver ting differential LVPECL clock input. Inver ting differential LVPECL clock input. Pulldown Non-inver ting differential LVPECL clock input. Pulldown Non-inver ting differential LVPECL clock input. Synchronizing control for enabling and disabling clock outputs. Pullup LVCMOS interface levels. Output enable. Controls enabling and disabling of outputs Pullup Q0 thru Q23. No connect. TABLE 1. PIN DESCRIPTIONS Number 1, 2, 5, 6 7, 8, 11, 12 3, 9, 28, 34, 39, 45 4, 10, 14,18, 27, 33, 40, 46 13 15, 19 16 17 20 21 22 23 Name Q16, Q17, Q18, Q19 Q20, Q21, Q22, Q23 VDDO GND CLK_SEL VDD nCLK1 CLK1 nCLK0 CLK0 CLK_EN OE www.DataSheet4U.com 24 nc Unused 25, 26, 29, 30 Q0, Q1, Q2, Q3 Output Q0 thru Q7 outputs. 7Ω typical output impedance. 31, 32, 35, 36 Q4, Q5, Q6, Q7 37, 38, 41, 42 Q8, Q9, Q10, Q11 Output Q8 thru Q15 outputs. 7Ω typical output impedance. 43, 44, 47, 48 Q12, Q13, Q14, Q15 NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol CIN Parameter Input Capacitance CLK0, nCLK0, CLK1, nCLK1 CLK-SEL, CLK_EN, OE Test Conditions Minimum Typical Maximum 4 4 Units pF pF pF CPD RPULLUP RPULLDOWN ROUT Power Dissipation Capacitance (per output) Input Pullup Resistor Input Pulldown Resistor Output Impedance 51 51 7 pF pF KΩ KΩ Ω 8344AY-01 www.icst.com/products/hiperclocks.html 2 REV. B AUGUST 6, 2001 Integrated Circuit Systems, Inc. ICS8344-01 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER Bank 2 Bank 3 Output Q8-Q15 Hi-Z Enabled Input OE 0 1 Output Q16-Q23 Hi-Z Enabled TABLE 3A. OUPUT ENABLE FUNCTION TABLE Bank 1 Input OE 0 1 www.DataSheet4U.com Output Q0-Q7 Hi-Z Enabled Input OE 0 1 TABLE 3B. CLOCK SELECT FUNCTION TABLE Control Input CLK_SEL 0 1 CLK0, nCLK0 Selected De-selected Clock CLK1, nCLK1 De-selected Selected TABLE 3C. CLOCK INPUT FUNCT.


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