NETWORK SEARCH ENGINE
128K x 72 Entries
To request the full IDT75K62100 datasheet, please contact your local
IDT Sales Representative or call 1-831-754-4555
IDT provides proven, industry-leading network search engines
(NSEs) and a comprehensive suite of software that enable and accelerate
the intelligent processing of network services in communications equip-
ment. As a part of the complete IDT classification subsystem that includes
content inspection engines, the IDT family of NSEs delivers high-
www.DataSheept4eUrf.ocrommance, feature-rich, easy-to-use, integrated search accelerators.
synchronous full-ternary 128K x 72 entry device. Each entry location in
the NSE has both a Data entry and an associated Mask entry. The NSE
devices integrate content addressable memory (CAM) technology with
high-performance logic. They can perform Lookup and Learn NSE
operations plus Read, Write, Burst Write, and Dual Write maintenance
The IDT 75K62100 NSE device has a bi-directional bus that is a
multiplexed address and data bus that can support 100 million sustained
searches per second. This device provides array segments which can
be configured to enable multiple width lookups from 36 to 576 bits wide.
The IDT 75K62100 requires a 1.2-volt VDD supply and a 2.5-volt VDDQ
supply. This NSE device provides the user with flexibility and control in
for a specific NSE operation are powered up while the unused segments
The IDT 75K62100 utilizes the latest high-performance 1.2V CMOS
processing technology and is packaged in a JEDEC Standard, thermally
enhanced, low profile Ball Grid Array. The IDT 372 BGA package
372 BGA footprint is backwards compatible with the IDT 64K x 72 Entry
(75P52100) and 32K x 72 Entry (75P42100) NSE devices.
Ram Control Circuits
Global Mask Registers
5334 drw 01
The IDT NSEs are designed to fulfill the needs of various types of
networking systems. In solutions requiring data searching such as
routers, a system configuration as shown in Figure 1.0 may be realized.
Maximum flexibility is provided by allowing one board design to be
populated today using either the IDT 75P42100 or 75P52100 NSEs and
later upgraded to use the IDT 75K62100 NSE. Applications note AN-279
discusses how to accommodate one board design for any of these NSEs.
In this compatible configuration, the NSE interfaces directly to an
ASIC/ FPGA for lookups and routes an Index to an associated SRAM
device, which supplies the next hop address via an SRAM Data Bus to
the ASIC. The NSE provides the required control signals to directly
can also be fed directly back to the ASIC/ FPGA without the use of external
SRAM. Control of the associated handshake signals is provided by all
NSEs to adapt to either configuration.
Figure 1.0 ASIC / Compatible NSE / SRAM configuration
Network Search Engine
© 2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.