MCF5329

Freescale Semiconductor Data Sheet: Technical Data MCF532x ColdFire® Microprocessor Data Sheet Features Version 3 ColdFire variable-length RISC processor core System debug support JTAG support for system level board testing On-chip memories – 16-Kbyte unified write-back cache – 32-Kbyte dual-ported SRAM on CPU internal bus, accessible by core and non-core bus masters (e.g., DMA, FEC, LCD controller, and USB host and OTG) Power management Liquid Crystal Display Controller (LCDC) Embedded Voice-over-IP (VoIP) system solution SDR/DDR SDRAM Controller Universal Serial Bus (USB) Host Controller Universal Serial Bus (USB) On-the-Go (OTG) controller Synchronous Serial Interface (SSI) Fast Ethernet Controller (FEC) Cryptography Hardware Accelerators FlexCAN Module Three Universal Asynchronous Receiver Transmitters (UARTs) I2C Module Queued Serial Peripheral Interface (QSPI) Pulse Width Modulation (PWM) module Real Time Clock Four 32-bit DMA Timers Software Watchdog Timer Four Periodic Interrupt Timers (PITs) Phase Locked Loop (PLL) Interrupt Controllers (x2) DMA Controller FlexBus (External Interface) Chip Configuration Module (CCM) Reset Controller General Purpose I/O interface Document Number: MCF5329DS Rev. 5, 11/2008 MCF5329 MAPBGA–256 17mm x 17mm MAPBGA–196 15mm x 15mm © Freescale Semiconductor, Inc., 2008. All rights reserved. Table of Contents 1 MCF532x Family Comparison . . . . . . . . . . . . . . . . . . . . . ...