LH6V4256

LH6V4256 FUNCTION 262,144 words × 4 bit Access time: 100 ns (MAX) Cycle time: 190 ns (MIN) Fast page mode cycle time: 60 ns (MIN) Power supply: +3.3 V ±0.3 V Power consumption (MAX): Operating: 126 mW Standby: 0.54 mW Built-in latch circuit for row-address, column-address, and input data OE = Don’t care in early write operation RAS only refresh, hidden refresh, and CAS before RAS refresh capability On-chip refresh counter 512 refresh cycle/8 ms Packages: 20-pin, 300-mil DIP 26-pin, 300-mil SOJ 28-pin, 8 × 13 mm2 TSOP (Type I) CMOS 1M (256K × 4) Dynamic RAM DESCRIPTION The LH6V4256 is a 262,144 word × 4-bit dynamic RAM which allows fast page mode access. The LH6V4256 is fabricated on SHARP’s advanced CMOS double-level polysilicon gate technology. With its input multiplexed and packaged in the standard 20-pin DIP, 26-pin SOJ, or 28-pin TSOP (I) packages, it is easy to realize memory systems with low power dissipation and large memory capacity. The LH6V4256 operates on a single +3.3 V power supply and the built-in biasing voltage generator circuit. PIN CONNECTIONS 20-PIN DIP I/O1 I/O2 WE RAS NC A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VSS I/O 4 I/O3 CAS OE A8 A7 A6 A5 A4 6V4256-1 TOP VIEW Figure 1. Pin Connections for DIP Package 2-14 CMOS 1M (256K × 4) Dynamic RAM LH6V4256 26-PIN SOJ I/O1 I/O2 WE RAS NC 1 2 3 4 5 26 25 24 23 22 VSS I/O4 I/O3 CAS OE TOP VIEW 28-PIN TSOP (Type I) TOP VIEW NC OE CAS I/O3 I/O4 VSS NC NC ...