LH5PV8512

LH5PV8512 FEATURES 524,288 words × 8 bit organization CE access time (tCEA): 120 ns (MAX.) Cycle time (tRC): 190 ns (MIN.) Power supply: +3.0 V ± 0.15 V (Operating) +2.2 V to +3.15 V (Data retention) Power consumption (MAX.): 126 mW (Operating) 95 µW (Standby = CMOS input level) 221 µW (Self-refresh = CMOS input level) Available for address refresh, auto-refresh, and self-refresh modes 2,048 refresh cycles/32 ms Address non-multiple Not designed or rated as radiation hardened Package: 32-pin, 525-mil SOP Package material: Plastic Substrate material: P-type silicon Process: Silicon-gate CMOS Operating temperature: 0 - 70°C CMOS 4M (512K × 8) Pseudo-Static RAM DESCRIPTION The LH5PV8512 is a 4M bit Pseudo-Static RAM with a 524,288 word × 8 bit organization. It is fabricated using silicon-gate CMOS process technology. A PSRAM uses on-chip refresh circuitry with a DRAM memory cell for pseudo-static operation which eliminates external clock inputs, while having the same pinout as industry standard SRAMs. Moreover, due to the functional similarities between PSRAMs and SRAMs, existing 512K × 8 SRAM sockets can be filled with the LH5PV8512N with little or no changes. The advantage is the cost saving realized with the lower cost PSRAM. The LH5PV8512 has the ability to fill the gap between DRAM and SRAM by offering low cost, low power standby and simple interface. PIN CONNECTIONS 32-PIN SOP A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 ...