LH543621

LH543611/21 FEATURES Pin-Compatible and Functionally Upwards-Compatible with Sharp LH5420 and LH543601, but Deeper Expanded Control Register that is Fully Readable as well as Writeable Fast Cycle Times: 18/20/25/30/35 ns Improved Input Setup and Flag Out Timing Two 512 × 36-bit FIFO Buffers (LH543611) or Two 1024 × 36-bit FIFO Buffers (LH543621) Full 36-bit Word Width Selectable 36/18/9-bit Word Width on Port B; Selection May be Changed Without Resetting the BiFIFO Programmable Byte-Order Reversal – ‘Big-Endian ↔ Little-Endian Conversion’ Independently-Synchronized (‘Fully-Asynchronous’) Operation of Port A and Port B ‘Synchronous’ Enable-Plus-Clock Control at Both Ports R/W, Enable, Request, and Address Control Inputs are Sampled on the Rising Clock Edge Synchronous Request/Acknowledge ‘Handshake’ Capability; Use is Optional Device Comes Up Into a Known Default State at Reset; Programming is Allowed, but is not Required Asynchronous Output Enables Five Status Flags per Port: Full, Almost-Full, Half-Full, Almost-Empty, and Empty All Flags are Independently Programmable for Either Synchronous or Asynchronous Operation Almost-Full Flag and Almost-Empty Flag Have Programmable Offsets Mailbox Registers with Synchronized Flags Data-Bypass Function Data-Retransmit Function Automatic Byte Parity Checking with Programmable Parity Flag Latch Programmable Byte Parity Generation Programmable Byte, Half-Word, or Full-Word Oriented Parit...