LH540205

LH540205 FEATURES Fast Access Times: 20/25/35/50 ns Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology Input Port and Output Port Have Entirely Independent Timing Expandable in Width and Depth Full, Half-Full, and Empty Status Flags Data Retransmission Capability TTL-Compatible I/O Pin and Functionally Compatible with Am/IDT7205 Control Signals Assertive-LOW for Noise Immunity Package: 28-Pin, 300-mil PDIP CMOS 8192 × 9 Asynchronous FIFO Data words are read out from the LH540205’s output port in precisely the same order that they were written in at its input port; that is, according to a First-In, First Out (FIFO) queue discipline. Since the addressing sequence for a FIFO device’s memory is internally predefined, no external addressing information is required for the operation of the LH540205 device. Drop-in-replacement compatibility is maintained with both larger sizes and smaller sizes of industry-standard nine-bit asynchronous FIFOs. The only change is in the number of internally-stored data words implied by the states of the Full Flag and the Half-Full Flag. The Retransmit (RT) control signal causes the internal FIFO-memory-array read-address pointer to be set back to zero, to point to the LH540205’s first physical memory location, without affecting the internal FIFO-memoryarray write-address pointer. Thus, the Retransmit control signal provides a mechanism whereby a block of data, delimited by the zero physical address and th...