High-Performance Surface-Mount TTL Delay Lines
n Five equal taps in 20% increments of total delay. n Lumped constant, ac...
High-Performance Surface-Mount TTL Delay Lines
n Five equal taps in 20% increments of total delay. n Lumped constant, active series. www.DataSheet4U.com n Transfer-molded packaging for highest reliability. n Designed for leading edge timing. Trailing edge
CTTLDL, BJTTLDL, GBTTLDL, BTTLDL
n Military models with temperature range -55 to
timing available.
n Supports
Schottky TTL, FAST, and FACT logics. n Fanout 1 -- 20 loads; logic 0 -- 10 loads. n Temperature coefficient +2 ns or +4% (whichever is
greater) at maximum delay, 0 to 70oC.
+125oC and ceramic package IC to meet MIL-STD883C, but not screened to that specification, add suffix “M” to part number. n Military models as above, but with ceramic package IC screened to MIL-STD 883C and 38510, add suffix “MX” to part number. n Military models as “MX” above, but with in-house burn-in and thermal shock, add suffix “MY”.
LOW PROFILE SURFACE-MOUNT 5-TAP TTL DELAY LINES
TAP D ELA YS (ns) T ECH NITROL PART NO.
CT TLDL025 CT TLDL050 CT TLDL075 CT TLDL100 CT TLDL125 CT TLDL150 CT TLDL200
ALL TAPS
O.175” MAX HEIGHT
TD D1
5.0 10.0 15.0 20.0 25.0 30.0 40.0
TD D2
10.0 20.0 30.0 40.0 50.0 60.0 80.0
TD D3
15.0 30.0 45.0 60.0 75.0 90.0 120.0
TD D4
20.0 40.0 60.0 80.0 100.0 120.0 160.0
TD D5
25.0 50.0 75.0 100.0 125.0 150.0 200.0
TRO RO
2.0 2.0 2.0 2.0 2.0 2.0 2.0
TFO FO
2.0 2.0 2.0 5.0 5.0 6.0 7.0
For TTL delay lines qualified to MIL-D-83532, refer to PSC information sheet entitled “QPL Active Delay Lines.”
Delay Characterist...
