LH532048

LH532048 FEATURES 131,072 words × 16 bit organization Access time: 100 ns (MAX.) Static operation TTL compatible I/O Three-state outputs Single +5 V power supply Power consumption: Operating: 412.5 mW (MAX.) Standby: 550 µW (MAX.) Packages: 40-pin, 600-mil DIP 40-pin, 525-mil SOP 44-pin, 650-mil QFJ (PLCC) DESCRIPTION The LH532048 is a 2M-bit mask-programmable ROM organized as 131,072 × 16 bits. It is fabricated using silicon-gate CMOS process technology. 40-PIN DIP 40-PIN SOP CMOS 2M (128K × 16) MROM PIN CONNECTIONS TOP VIEW NC CE D15 D14 D13 D12 D11 D10 D9 D8 GND D7 D6 D5 D4 D3 D2 D1 D0 OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC NC A16 A15 A14 A13 A12 A11 A10 A9 GND A8 A7 A6 A5 A4 A3 A2 A1 A0 532048-1 Figure 1. Pin Connections for DIP and SOP Packages 44-PIN PLCC VCC D13 D14 D15 A16 A15 A14 NC NC NC CE TOP VIEW 6 D12 D11 D10 D9 D8 GND NC D7 D6 D5 D4 7 8 9 10 11 12 13 14 15 16 17 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 A13 A12 A11 A10 A9 GND NC A8 A7 A6 A5 18 19 20 21 22 23 24 25 26 27 28 D3 D2 D1 D0 A0 A1 A2 A3 OE NC A4 532048-2 Figure 2. Pin Connections for QFJ (PLCC) Package 1 LH532048 CMOS 2M MROM A16 38 A15 37 A14 36 A13 35 A12 34 3 D15 MEMORY MATRIX (131,072 x 16) 4 D14 5 D13 6 D12 7 D11 8 D10 OUTPUT BUFFER A9 A8 A7 A6 31 29 28 27 ADDRESS BUFFER A11 33 A10 32 ADDRESS DECODER 9 D9 10 D8 12 D7 13 D6 14 D5 15 D4 16 D3 17 D2 18 D1 A5 26 ...