LH530800A-Y

LH530800A-Y FEATURES 131,072 words × 8 bit organization Access times: 500 ns (MAX.) at 2.6 V ≤ VCC < 4.5 V 150 ns (MAX.) at 4.5 V ≤ VCC ≤ 5.5 V Low-power consumption: Operating: 193 mW (MAX.) Standby: 550 µW (MAX.) Static operation Three-state outputs Mask-programmable control pin: Pin 24 = OE/OE Wide range power supply: 2.6 V to 5.5 V Packages: 32-pin, 600-mil DIP 32-pin, 525-mil SOP DESCRIPTION The LH530800A-Y is a 1M-bit mask-programmable ROM organized as 131,072 × 8 bits. It is fabricated using silicon-gate CMOS process technology. CMOS 1M (128K × 8) 3 V-Drive MROM PIN CONNECTIONS 32-PIN DIP 32-PIN SOP NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Vcc NC NC A14 A13 A8 A9 A11 OE/OE A10 CE D7 D6 D5 D4 D3 TOP VIEW 530800A-Y-1 Figure 1. Pin Connections for DIP and SOP Packages 1 LH530800A-Y CMOS 1M Mask-Programmable ROM A16 1 A15 2 A14 28 ADDRESS DECODER A10 22 A9 25 A8 26 A7 4 A6 5 A5 6 A4 A3 A2 A1 7 8 9 10 ADDRESS BUFFER A13 27 A12 3 A11 24 MEMORY MATRIX (131,072 x 8) COLUMN SELECTOR A0 11 SENSE AMPLIFIER CE 21 CE BUFFER TIMING GENERATOR OUTPUT BUFFER OE/OE 23 OE BUFFER 30 31 VCC 15 GND 12 D0 13 D1 14 D2 16 D3 17 D4 18 D5 19 D6 20 D7 530800A-Y-2 Figure 2. LH530800A-Y Block Diagram PIN DESCRIPTION SIGNAL PIN NAME NOTE SIGNAL PIN NAME NOTE A0 - A16 D0 - D7 CE OE/OE Address input Data Output Chip enable input Output enable input 1 VCC GND NC Pow...