MT47H256M8

2Gb: x4, x8, x16 DDR2 SDRAM Features DDR2 SDRAM MT47H512M4 – 64 Meg x 4 x 8 banks MT47H256M8 – 32 Meg x 8 x 8 banks MT47H128M16 – 16 Meg x 16 x 8 banks Features www.DataSheet4U.com Vdd = +1.8V ±0.1V, VddQ = +1.8V ±0.1V JEDEC-standard 1.8V I/O (SSTL_18-compatible) Differential data strobe (DQS, DQS#) option 4n-bit prefetch architecture Duplicate output strobe (RDQS) option for x8 DLL to align DQ and DQS transitions with CK 8 internal banks for concurrent operation Programmable CAS latency (CL) Posted CAS additive latency (AL) WRITE latency = READ latency - 1 tCK Programmable burst lengths: 4 or 8 Adjustable data-output drive strength 64ms, 8,192-cycle refresh On-die termination (ODT) Industrial temperature (IT) option RoHS compliant Supports JEDEC clock jitter specification Configuration – 512 Meg x 4 (64 Meg x 4 x 8 banks) – 256 Meg x 8 (32 Meg x 8 x 8 banks) – 128 Meg x 16 (16 Meg x 16 x 8 banks) FBGA package (Pb-free) – x16 – 84-ball FBGA (11.5mm x 14mm) Rev. A FBGA package (Pb-free) – x4, x8 – 60-ball FBGA (11.5mm x 14mm) Rev. A Timing – cycle time – 3.0ns @ CL = 4 (DDR2-667) – 3.0ns @ CL = 5 (DDR2-667) – 3.75ns @ CL = 4 (DDR2-533) – 5.0ns @ CL = 3 (DDR2-400) Self refresh – Standard – Low-power Operating temperature – Commercial (0°C ≤ TC ≤ 85°C) – Industrial (–40°C ≤ TC ≤ 95°C; –40°C ≤ TA ≤ 85°C) Revision Note: Options1 Marking 512M4 256M8 128M16 HG HG -3E -3 -37E -5E None L None IT :A 1. Not all options listed can be...