Document
HD49340F/HF
CDS/PGA & 10-bit A/D Converter
REJ03F0108-0100Z Rev.1.0 Apr 20, 2004
Description
The HD49340F/HF is a CMOS IC that provides CDS-PGA analog processing (CDS/PGA) suitable for CCD camera digital signal processing systems together with a 10-bit A/D converter in a single chip.
www.DataSheet4U.com
Functions
• • • • • • • Correlated double sampling PGA Offset compensation Serial interface control 10-bit ADC Operates using only the 3 V voltage Corresponds to switching mode of power dissipation and operating frequency Power dissipation: 120 mW (Typ), maximum frequency: 36 MHz (HD49340HF) Power dissipation: 60 mW (Typ), maximum frequency: 25 MHz (HD49340F) • ADC direct input mode • QFP 48-pin package
Features
• Suppresses low-frequency noise output from CCD by the S/H type correlated double sampling. • The S/H response frequency characteristics for the reference level can be adjusted using values of external parts and registers. • High sensitivity is achieved due to the high S/N ratio and a wide coverage provided by a PG amplifier. • Feedback is used to compensate and reduce the DC offsets including the output DC offset due to PGA gain change and the CCD offset in the CDS (correlated double sampling) amplifier input. • PGA, standby mode, etc., is achieved via a serial interface. • High precision is provided by a 10-bit-resolution A/D converter.
Rev.1.0, Apr 20, 2004, page 1 of 22
HD49340F/HF
Pin Arrangement
ADCIN AVSS NC AVDD BIAS BLKC CDSIN BLKFB BLKSH AVDD AVSS AVSS
www.DataSheet4U.com
VRM VRT VRB NC DVSS OEB DVDD DVDD DVSS CS SDATA SCK
36 35 34 33 32 31 30 29 28 27 26 25 37 24 38 23 39 22 40 21 41 20 42 19 43 18 44 17 16 45 46 15 47 14 48 13 1 2 3 4 5 6 7 8 9 10 11 12
NC NC SPSIG SPBLK OBP PBLK DVDD DVDD ADCLK DVSS DVSS DRDVDD
Pin Description
Pin No. 1 2 to 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Symbol NC D0 to D9 NC DRDVDD DVSS DVSS ADCLK DVDD DVDD PBLK OBP SPBLK SPSIG NC NC AVSS AVSS AVDD BLKSH BLKFB CDSIN BLKC Description No connection pin Digital output No connection pin Output buffer power supply (3 V) Digital ground (0 V) Digital ground (0 V) ADC conversion clock input pin Digital power supply (3 V) Digital power supply (3 V) Preblanking input pin Optical black pulse input pin Black level sampling clock input pin Signal level sampling clock input pin No connection pin No connection pin Analog ground (0 V) Analog ground (0 V) Analog power supply (3 V) Black level S/H pin Black level FB pin CDS input pin Black level C pin I/O — O — — — — I — — I I I I — — — — — — — I — Analog(A) or Digital(D) — D — D D D D D D D D D D — — A A A A A A A
Rev.1.0, Apr 20, 2004, page 2 of 22
NC D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 NC
(Top view)
HD49340F/HF
Pin Description (cont.)
Pin No. 32 33 34 35 36 37 38
www.DataSheet4U.com
Symbol BIAS AVDD NC AVSS ADCIN VRM VRT VRB NC DVSS 1 OEB * DVDD DVDD DVSS CS SDATA SCK
Description Internal bias pin Connect a 33 kΩ resistor between BIAS and AVSS. Analog power supply (3 V) No connection pin Analog ground (0 V) ADC input pin Reference voltage pin 1 Connect a 0.1 µF ceramic capacitor between VRM and AVSS. Reference voltage pin 3 Connect a 0.1 µF ceramic capacitor between VRT and AVSS. Reference voltage pin 2 Connect a 0.1 µF ceramic capacitor between VRB and AVSS. No connection pin Digital ground (0 V) Digital output enable pin Digital power supply (3 V) Digital power supply (3 V) Digital ground (0 V) Serial interface control input pin Serial data input pin Serial clock input pin
I/O — — — — — — — — — — — — — — I I I
Analog(A) or Digital(D) A A — A A A A A — D D D D D D D D
39 40
41 42 43 44 45 46 47 48 Note:
1. With pull-down resistor.
Rev.1.0, Apr 20, 2004, page 3 of 22
HD49340F/HF
Input/Output Equivalent Circuit
Pin Name Digital output D0 to D9 Equivalent Circuit
DIN STBY
Digital input ADCLK, OBP, SPBLK, SPSIG, CS, SCK, SDATA, PBLK, OEB DVDD Digital input *1
DVDD Digital output
Note: Only OEB is pulled down to about 70 kΩ. Analog
www.DataSheet4U.com
CDSIN
AVDD CDSIN
Internally connected to VRT
ADCIN
ADCIN
AVDD
Internally connected to VRM
BLKSH, BLKFB, BLKC
BLKFB
AVDD
+ −
BLKSH BLKC
VRT, VRM, VRB VRT
+ −
+ −
VRM VRB AVDD
+ −
BIAS
BIAS
AVDD
Rev.1.0, Apr 20, 2004, page 4 of 22
HD49340F/HF
Block Diagram
DRDVDD ADCLK SPBLK SPSIG DVDD AVDD DVSS AVSS
16 18 19 Timing generator
31 16 18 19 19 42 OEB
ADCIN 27 PBLK 26 CDSIN 26 BLKSH 28
www.DataSheet4U.com
9 D9 CDS PGA 10-bit ADC 8 D8 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 D1 D0
BLKC 28
BLKFB 29
DC offset compensation circuit
Serial interface
Bias generator
17
44 45 43
35
32 34 33
VRT
VRM
SDATA
Rev.1.0, Apr 20, 2004, page 5 of 22
BIAS
OBP
VRB
SCK
CS
Output latch circuit
HD49340F/HF
Internal Functions
Functional Description • CDS input CCD low-frequency noise is suppressed by CDS (correlated double sampling). The signal level is clamped at 14 LSB to 76 LSB by resister during the OB period. *1 Gain can be adjusted using 8 bits of register (0.132 dB steps) wit.