UT54ACS74

UT54ACS74/UT54ACTS74 Radiation-Hardened Dual D Flip-Flops with Clear & Preset FEATURES radiation-hardened CMOS - Latchup immune High speed Low power consumption www.DataSheet4U.com Single 5 volt supply Available QML Q or V processes Flexible package - 14-pin DIP - 14-lead flatpack DESCRIPTION The UT54ACS74 and the UT54ACTS74 contain two independent D-type positive triggered flip-flops. A low level at the Preset or Clear inputs sets or resets the outputs regardless of the levels of the other inputs. When Preset and Clear are inactive (high), data at the D input meeting the setup time requirement is transferred to the outputs on the positive-going edge of the clock pulse. Following the hold time interval, data at the D input may be changed without affecting the levels at the outputs. The devices are characterized over full military temperature range of -55 C to +125 C. FUNCTION TABLE INPUTS PRE L H L H H H CLR H L L H H H L CLK X X X D X X X H L X OUTPUT Q H L H 1 PINOUTS 14-Pin DIP Top View CLR1 D1 CLK1 PRE1 Q1 Q1 VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD CLR2 D2 CLK2 PRE2 Q2 Q2 14-Lead Flatpack Top View CLR1 D1 CLK1 PRE1 Q1 Q1 VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD CLR2 D2 CLK2 PRE2 Q2 Q2 Q L H H L H Qo 1 LOGIC SYMBOL PRE1 CLK1 D1 CLR1 PRE2 CLK2 D2 CLR2 (4) (3) (2) (1) (10) (11) (12) (13) (9) (8) Q2 Q2 S C1 D1 R (5) (6) Q1 Q1 H L Qo Note: 1. The output levels in this configuration are not guaranteed to meet the minimum levels for VOH if the lows at pr...