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LH28F320S3TD-L10 Dataheets PDF



Part Number LH28F320S3TD-L10
Manufacturers Sharp Electrionic Components
Logo Sharp Electrionic Components
Description 32 M-bit (2 MB x 8/1 MB x 16 x 2-Bank) Smart 3 Dual Work Flash Memory
Datasheet LH28F320S3TD-L10 DatasheetLH28F320S3TD-L10 Datasheet (PDF)

LH28F320S3TD-L10 LH28F320S3TD-L10 DESCRIPTION The LH28F320S3TD-L10 Dual Work flash memory with Smart 3 technology is a high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications, having high programming performance is achieved through highly-optimized page buffer operations. Its symmetrically-blocked architecture, flexible voltage and enhanced cycling capability provide for highly flexible component suitable for resident flash arrays, SIMMs and memory card.

  LH28F320S3TD-L10   LH28F320S3TD-L10



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LH28F320S3TD-L10 LH28F320S3TD-L10 DESCRIPTION The LH28F320S3TD-L10 Dual Work flash memory with Smart 3 technology is a high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications, having high programming performance is achieved through highly-optimized page buffer operations. Its symmetrically-blocked architecture, flexible voltage and enhanced cycling capability provide for highly flexible component suitable for resident flash arrays, SIMMs and memory cards. Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F320S3TD-L10 offers three levels of protection : absolute protection with VPP at GND, selective hardware block locking, or flexible software block locking. These alternatives give designers ultimate control of their code security needs. LH28F320S3TD-L10 is conformed to the flash Scalable Command Set (SCS) and the Common Flash Interface (CFI) specification which enable universal and upgradable interface, enable the highest system/device data transfer rates and minimize device and system-level implementation costs. 32 M-bit (2 MB x 8/1 MB x 16 x 2-Bank) Smart 3 Dual Work Flash Memory • Scalable Command Set (SCS) • High performance read access time – 100 ns (3.3±0.3 V)/120 ns (2.7 to 3.6 V) • Enhanced automated suspend options – Write suspend to read – Block erase suspend to write – Block erase suspend to read • Enhanced data protection features – Absolute protection with VPP = GND – Flexible block locking – Erase/write lockout during power transitions • SRAM-compatible write interface • User-configurable x8 or x16 operation • High-density symmetrically-blocked architecture – Sixty-four 64 k-byte erasable blocks • Enhanced cycling capability – 100 000 block erase cycles – 3.2 million block erase cycles/bank • Low power management – Deep power-down mode – Automatic power saving mode decreases Icc in static mode • Automated write and erase – Command user interface – Status register • ETOXTM∗ V nonvolatile flash technology • Package – 56-pin TSOP Type I (TSOP056-P-1420) Normal bend ∗ ETOX is a trademark of Intel Corporation. FEATURES • Smart 3 Dual Work technology – 2.7 V or 3.3 V VCC – 2.7 V, 3.3 V or 5 V VPP – Capable of performing erase, write and read for each bank independently (Impossible to perform read from both banks at a time). • High-speed write performance – Two 32-byte page buffers/bank – 2.7 µs/byte write transfer rate • Common Flash Interface (CFI) – Universal & upgradable interface In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device. -1- LH28F320S3TD-L10 PIN CONNECTIONS 56-PIN TSOP (Type I) NC BE1L# BE1H# A20 A19 A18 A17 A16 VCC A15 A14 A13 A12 BE0# VPP RP# A11 A10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 TOP VIEW WP# WE# OE# STS DQ15 DQ7 DQ14 DQ6 GND DQ13 DQ5 DQ12 DQ4 VCC GND DQ11 DQ3 DQ10 DQ2 VCC DQ9 DQ1 DQ8 DQ0 A0 BYTE# NC NC (TSOP056-P-1420) -2- LH28F320S3TD-L10 BLOCK DIAGRAM Bank1 Bank0 OUTPUT BUFFER DQ0-DQ15 INPUT BUFFER OUTPUT MULTIPLEXER QUERY ROM DATA REGISTER IDENTIFIER REGISTER STATUS REGISTER DATA REGISTER I/O LOGIC VCC BYTE# BE0# BE1H# COMMAND USER INTERFACE WE# OE# RP# WP# BE0# BE1L# MULTIPLEXER DATA COMPARATOR A0-A20 INPUT BUFFER Y DECODER Y GATING WRITE STATE MACHINE PROGRAM/ERASE VOLTAGE SWITCH STS VPP ADDRESS LATCH X DECODER 32 64 k-BYTE BLOCKS VCC GND ADDRESS COUNTER -3- LH28F320S3TD-L10 PIN DESCRIPTION SYMBOL TYPE NAME AND FUNCTION ADDRESS INPUTS : Inputs for addresses during read and write operations. Addresses are internally latched during a write cycle. A0 : Byte Select Address. Not used in x16 mode (can be floated). A1-A4 : Column Address. Selects 1 of 16-bit lines. A5-A15 : Row Address. Selects 1 of 2 048-word lines. A16-A20 : Block Address. DATA INPUT/OUTPUTS : DQ0-DQ7 : Inputs data and commands during CUI write cycles; outputs data during memory array, status register, query, and identifier code read cycles. Data pins float to high-impedance when the chip is deselected or outputs are disabled. Data is internally latched during a write cycle. DQ8-DQ15 : Inputs data during CUI write cycles in x16 mode; outputs data during memory array read cycles in x16 mode; not used for status register, query and identifier code read mode. Data pins float to high-impedance when the chip is deselected, outputs are disabled, or in x8 mode (BYTE# = VIL). Data is internally latched during a write cycle. BANK ENABLE : Activates the devi.


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