ASM4SSTVF16859

August 2004 rev 2.0 DDR 13-Bit to 26-Bit Registered Buffer ASM4SSTVF16859 off. Note that RESETB should be supported with a Features   Differential clock signals. Meets SSTL_2 class II specifications on outputs.  www.DataSheet4U.com LVCMOS level at a valid state since VREF may not be stable during power-up. To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESETB must be held at a logic low level during power-up. Low voltage operation: VDD = 2.3V to 2.7V. Available in 64-pin TSSOP, 64-pin TVSOP, and 56-pin VFQFN packages.  Product Description The ASM4SSTVF16859 is a universal 13/26 bit register (D F/F based), designed for 2.3V to 2.7V In the JEDEC defined Registered DDR DIMM application, RESETB is specified to be asynchronous with respect to CLK/CLKB; therefore, no timing relationship can be guaranteed between the two signals. When entering a low-power standby state, the register will be cleared and the outputs will be driven to a logic low level quickly relative to the time to disable the differential input receivers. This ensures there are no “glitches” on any output. However, when coming out of low power standby mode, the register will become active quickly relative to the time taken to enable the differential input receivers. When the data inputs are at a logic level low and the clock is stable during the low-to-high transition of RESETB until the VDD operation. The device supports SSTL_2 I/O levels, and is fully com...