ASM4SSTVF16857

August 2004 rev 2.0 DDR 14-Bit Registered Buffer ASM4SSTVF16857 LVCMOS level at a valid logic state since VREF may Features Fully JEDEC JC40 - JC42.5 compliant for DDR1 applications to include: PC1600, PC2100, PC2700 & PC3200 ( > JEDEC defined DDR 400 @ 200MHz ) www.DataSheet4U.com Low voltage operation; VDD: 2.3V - 2.7V. not be stable during power-up. To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESETB must be held at a logic low level during power-up. In the JEDEC defined Registered DDR DIMM SSTL_2 Class II outputs. Differential clock inputs. Available in 48 pin TSSOP and TVSOP packages. application, RESETB is specified to be asynchronous with respect to CLK/CLKB; therefore, no timing relationship can be guaranteed between the two Product Description The ASM4SSTVF16857 is a universal 14-bit register (D F/F based), designed for 2.3V to 2.7V VDD . The device supports SSTL_2 I/O levels, and is fully compliant with the JEDEC JC40, JC42.5 DDR I specifications covering PC1600, PC2100, PC2700, and PC3200 operational ranges. 14-bit refers to 2Q outputs for each D input - designed for use in Stacked Registers (stacked memory devices), Buffered DIMM applications. Data flow from D to Q is controlled by the differential clock (CLK/CLKB) along with a controlled reset (RESETB). The positive edge of CLK is used to trigger the data transfer, and CLKB is used to maintain sufficient noise margins, whereas the RESETB input is d...