DatasheetsPDF.com

AS7C251MFT36A Dataheets PDF



Part Number AS7C251MFT36A
Manufacturers Alliance Semiconductor Corporation
Logo Alliance Semiconductor Corporation
Description (AS7C251MFT32A / AS7C251MFT36A) 2.5V 1M x 32/36 Flow-through synchronous SRAM
Datasheet AS7C251MFT36A DatasheetAS7C251MFT36A Datasheet (PDF)

January 2005 ® AS7C251MFT32A AS7C251MFT36A 2.5V 1M × 32/36 Flow-through synchronous SRAM Features • • • • • • • Organization: 1,048,576 words × 32 or 36 bits Fast clock to data access: 7.5/8.5/10 ns Fast OE access time: 3.5/4.0 ns Fully synchronous flow-through operation Asynchronous output enable control Available in 100-pin TQFP package Individual byte write and global write • • • • • Multiple chip enables for easy expansion 2.5V core power supply Linear or interleaved burst control Snooze m.

  AS7C251MFT36A   AS7C251MFT36A


Document
January 2005 ® AS7C251MFT32A AS7C251MFT36A 2.5V 1M × 32/36 Flow-through synchronous SRAM Features • • • • • • • Organization: 1,048,576 words × 32 or 36 bits Fast clock to data access: 7.5/8.5/10 ns Fast OE access time: 3.5/4.0 ns Fully synchronous flow-through operation Asynchronous output enable control Available in 100-pin TQFP package Individual byte write and global write • • • • • Multiple chip enables for easy expansion 2.5V core power supply Linear or interleaved burst control Snooze mode for reduced power-standby Common data inputs and data outputs www.DataSheet4U.com Logic block diagram LBO CLK ADV ADSC ADSP A[19:0] 20 CLK CE CLR Q0 Burst logic Q1 2 2 D Q CE Address register CLK D DQd Q Byte write registers CLK D DQ Q c Byte write registers CLK D DQb Q Byte write registers CLK D DQa Q Byte write registers CLK D Enable CE register CLK Q 1M × 32/36 Memory array 20 18 20 32/36 32/36 GWE BWE BWd BWc BWb BWa CE0 CE1 CE2 4 OE Output registers CLK Input registers CLK ZZ Power down D Enable Q delay register CLK 32/36 DQ[a:d] OE Selection guide Minimum cycle time Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) -75 8.5 7.5 325 130 90 -85 10 8.5 300 130 90 -10 12 10 275 130 90 Units ns ns mA mA mA 1/17/05, v 1.2 Alliance Semiconductor 1 of 19 Copyright © Alliance Semiconductor. All rights reserved. AS7C251MFT32A AS7C251MFT36A ® 2.5V 32 Mb Synchronous SRAM products list1,2 Org 2MX18 1MX32 1MX36 2MX18 1MX32 1MX36 2MX18 www.DataSheet4U.com 1MX32 1MX36 2MX18 1MX32 1MX36 2MX18 1MX32 1MX36 Part Number AS7C252MPFS18A AS7C251MPFS32A AS7C251MPFS36A AS7C252MPFD18A AS7C251MPFD32A AS7C251MPFD36A AS7C252MFT18A AS7C251MFT32A AS7C251MFT36A AS7C252MNTD18A AS7C251MNTD32A AS7C251MNTD36A AS7C252MNTF18A AS7C251MNTF32A AS7C251MNTF36A Mode PL-SCD PL-SCD PL-SCD PL-DCD PL-DCD PL-DCD FT FT FT NTD-PL NTD-PL NTD-PL NTD-FT NTD-FT NTD-FT Speed 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 7.5/8.5/10 ns 7.5/8.5/10 ns 7.5/8.5/10 ns 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 7.5/8.5/10 ns 7.5/8.5/10 ns 7.5/8.5/10 ns 1 Core Power Supply: VDD = 2.5V + 0.125V 2 I/O Supply Voltage: VDDQ = 2.5V + 0.125V PL-SCD PL-DCD FT NTD1-PL NTD-FT : : : : : Pipelined Burst Synchronous SRAM - Single Cycle Deselect Pipelined Burst Synchronous SRAM - Double Cycle Deselect Flow-through Burst Synchronous SRAM Pipelined Burst Synchronous SRAM with NTDTM Flow-through Burst Synchronous SRAM with NTDTM 1NTD: No Turnaround Delay. NTDTM is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property of their respective owners. 1/17/05, v 1.2 Alliance Semiconductor 2 of 19 AS7C251MFT32A AS7C251MFT36A ® Pin assignment 100-pin TQFP - top view A A CE0 CE1 BWd BWc BWb BWa CE2 VDD VSS CLK GWE BWE OE ADSC ADSP ADV A A NC/DQPc DQc0 DQc1 VDDQ VSSQ DQc2 DQc3 DQc4 DQc5 VSSQ VDDQ DQc6 DQc7 NC VDD NC VSS DQd0 DQd1 VDDQ VSSQ DQd2 DQd3 DQd4 DQd5 VSSQ VDDQ DQd6 DQd7 NC/DQPd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 www.DataSheet4U.com TQFP 14 x 20mm 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQPb/NC DQb7 DQb6 VDDQ VSSQ DQb5 DQb4 DQb3 DQb2 VSSQ VDDQ DQb1 DQb0 VSS NC VDD ZZ DQa7 DQa6 VDDQ VSSQ DQa5 DQa4 DQa3 DQa2 VSSQ VDDQ DQa1 DQa0 DQPa/NC Note: For pins 1, 30, 51, and 80, NC applies to the x32 configuration. DQPn applies to the x36 configuration. 1/17/05, v 1.2 LBO A A A A A1 A0 NC A VSS VDD A A A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Alliance Semiconductor 3 of 19 AS7C251MFT32A AS7C251MFT36A ® Functional description The AS7C251MFT32A/36A is a high-performance CMOS 32-Mbit synchronous Static Random Access Memory (SRAM) device organized as 1,048,576 words × 32 or 36 bits. Fast cycle times of 8.5/10/12 ns with clock access times (tCD) of 7.5/8.5/10 ns. Three chip enable (CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses. Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register when ADSP is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation, the data accessed by the current address registered in the address registers by the positive edge of CLK are carried to the data-out buffer. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on all subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled low and both address strobes are high. Burst mode is selectable with the LBO input. With www.D.


AS7C251MFT32A AS7C251MFT36A AS7C251MNTD18A


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)