Document
LH28F004SU-Z1
FEATURES
40-PIN TSOP
4M (512K × 8) Flash Memory
TOP VIEW
• 512K × 8 Word Configuration • 5 V Write/Erase Operation (5 V VPP)
– No Requirement for DC/DC Converter to Write/Erase
A16 A15 A14 A13 A12 A11 A9 A8 WE RP VPP RY/BY A18 A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
A17 GND NC NC A10 DQ7 DQ6 DQ5 DQ4 VCC VCC NC DQ3 DQ2 DQ1 DQ0 OE GND CE A0
• • • •
100 ns Maximum Access Time 32 Independently Lockable Blocks (16K) 100,000 Erase Cycles per Block Automated Byte Write/Block Erase – Command User Interface – Status Register » BY » Status Output – RY / – Erase Suspend for Read – Two-Byte Write – Full Chip Erase
• System Performance Enhancement
• Data Protection
– Hardware Erase/Write Lockout during Power Transitions – Software Erase/Write Lockout
• Independently Lockable for Write/Erase
on Each Block (Lock Block and Protect Set/Reset)
28F004SUT-Z1-1
Figure 1. TSOP Configuration
• 5 µA (Typ.) ICC in CMOS Standby • 0.2 µA (Typ.) Deep Power-Down • State-of-the-Art 0.55 µm ETOX™ Flash
Technology
• 40-pin, 1.2 mm × 10 mm × 20 mm TSOP
(Type I) Package
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LH28F004SU-Z1
4M (512K × 8) Flash Memory
DQ0 - DQ7
OUTPUT BUFFER
INPUT BUFFER
ID REGISTER
DATA QUEUE REGISTER
I/O LOGIC
OUTPUT MULTIPLEXER
CSR REGISTER
ESRs
CE OE CUI WE RP
DATA COMPARATOR
A0 - A18
INPUT BUFFER
Y-DECODER
Y GATING/SENSING
16KB BLOCK 30
16KB BLOCK 31
16KB BLOCK 0
16KB BLOCK 1
WSM
RY/BY
ADDRESS QUEUE LATCH
...
X-DECODER
...
ADDRESS COUNTER
...
PROGRAM/ ERASE VOLTAGE SWITCH
VPP
VCC GND
28F004SUT-Z1-2
Figure 2. LH28F004SU-Z1 Block Diagram
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4M (512K × 8) Flash Memory
LH28F004SU-Z1
PIN DESCRIPTION
SYMBOL TYPE NAME AND FUNCTION WORD-SELECT ADDRESSES: Select a word within one 16K block. These addresses are latched during Data Writes. BLOCK-SELECT ADDRESSES: Select 1 of 32 Erase blocks. These addresses are latched during Data Writes, Erase and Lock-Block operations. DATA INPUT/OUTPUT: Inputs data and commands during CUI write cycles. Outputs array, buffer, identifier or status data in the appropriate Read mode. Floated when the chip is de-selected or the outputs are disabled. CHIP ENABLE INPUT: Activate the device’s control logic, input buffers, decoders and sense amplifiers. CE » must be low to select the device. RESET/POWER-DOWN: RP » low places the device in a Deep Power-Down state. All circuits that burn static power, even those circuits enabled in standby mode, are turned off. When returning from Deep Power-Down, a recovery time of 550 ns is required to allow these circuits to power-up. When RP» goes low, any current or pending WSM operation(s) are terminated, and the device is reset. All Status Registers return to ready (with all status flags cleared). OUTPUT ENABLE: Gates device data through the output buffers when low. The outputs float to tri-state off when OE » is high. WRITE ENABLE: Controls access to the CUI, Data Queue Registers and Address Queue Latches. WE is active low, and latches both address and data (command or array) on its rising edge. READY/BUSY: Indicates status of the internal WSM. When low, it indicates that the WSM is busy performing an operation. When the WSM is ready for new operation or Erase is Suspended, or the device is in deep power-down mode RY»/BY » pin is floated. ERASE/WRITE POWER SUPPLY (5.0 V ±0.5 V): For erasing memory array blocks or writing words/bytes into the flash array. DEVICE POWER SUPPLY (5.0 V ±0.5 V): Do not leave any power pins floating. GROUND FOR ALL INTERNAL CIRCUITRY: Do not leave any ground pins floating. NO CONNECT: No internal connection to die, lead may be driven or left floating
A0 - A13 A14 - A18
INPUT INPUT
DQ0 - DQ7
INPUT/OUTPUT
CE »
INPUT
RP »
INPUT
OE »
INPUT
WE
INPUT
RY »/BY »
OPEN DRAIN OUTPUT
VPP VCC GND NC
SUPPLY SUPPLY SUPPLY
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LH28F004SU-Z1
4M (512K × 8) Flash Memory
INTRODUCTION
Sharp’s LH28F004SU-Z1 4M Flash Memory is a revolutionary architecture which enables the design of truly mobile, high performance, personal computing and communication products. With innovative capabilities, 5 V single voltage operation and very high read/write performance, the LH28F004SU-Z1 is also the ideal choice for designing embedded mass storage flash memory systems. The LH28F004SU-Z1 is a very high density, highest performance non-volatile read/write solution for solidstate storage applications. Its independently lockable 32 symmetrical blocked architecture (16K each) extended cycling, low power operation, very fast write and read performance and selective block locking provide a highly flexible memory component suitable for high density memory cards, Resident Flash Arrays and PCMCIA-ATA Flash Drives. The LH28F004SU-Z1’s single power supply operation enables the design of memory cards which can be read/written in 5.0 V systems. Its x8 architecture allows the optimization of memory to processor interface. The flexible block locking opti.